{"id":2227765,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227765/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260424083837.214947-7-adityag@linux.ibm.com/","project":{"id":69,"url":"http://patchwork.ozlabs.org/api/1.1/projects/69/?format=json","name":"QEMU powerpc development","link_name":"qemu-ppc","list_id":"qemu-ppc.nongnu.org","list_email":"qemu-ppc@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424083837.214947-7-adityag@linux.ibm.com>","date":"2026-04-24T08:38:33","name":"[v6,06/10] pnv/mpipl: Set thread entry size to be allocated by firmware","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2e13b5bf6ebc2fad50618e28174d2d4d0a18bac1","submitter":{"id":86610,"url":"http://patchwork.ozlabs.org/api/1.1/people/86610/?format=json","name":"Aditya Gupta","email":"adityag@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260424083837.214947-7-adityag@linux.ibm.com/mbox/","series":[{"id":501319,"url":"http://patchwork.ozlabs.org/api/1.1/series/501319/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=501319","date":"2026-04-24T08:38:28","name":"Implement MPIPL for PowerNV","version":6,"mbox":"http://patchwork.ozlabs.org/series/501319/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227765/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227765/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=jrfbzpBk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n 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b=jrfbzpBkNCtkS/U3rYnrCDUoMSHGlACbw\n kkaPqHz6Etmz73TeXOeEtmOEQh2FLjgoSaArZmPUxTezdl4EE5bL9ar1hbAEdxeO\n 2WuF3ysIWask8wR4f1JBv4u9lzdp3SLyoiKf3iVW1rD6uzfbk4QG94bdU1Qhxl3I\n UmwJeCr1/amW9OhI/7j7CujNHk+5rBGxEJlTABicaZNr2H2fIVz1p3sz1ihQtFYw\n Tfw6goc/EZFXh8gE96nKZlOl1/yhy44vmBTjFk0h8AM0pRCtuGHnRuhKp7W5J6np\n mdp+sCzH3dPwUiI3/kC0bVBL3E4XhOVUZ2KcQeZRuOf+LzD2hPG3A==","From":"Aditya Gupta ","To":"","Cc":", Hari Bathini ,\n Sourabh Jain ,\n Harsh Prateek Bora ,\n Nicholas Piggin ,\n Miles Glenn , Chinmay Rath ,\n Shivang Upadhyay ","Subject":"[PATCH v6 06/10] pnv/mpipl: Set thread entry size to be allocated by\n firmware","Date":"Fri, 24 Apr 2026 14:08:33 +0530","Message-ID":"<20260424083837.214947-7-adityag@linux.ibm.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260424083837.214947-1-adityag@linux.ibm.com>","References":"<20260424083837.214947-1-adityag@linux.ibm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-Reinject":"loops=2 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autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-ppc@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Set the \"Thread Register State Entry Size\" that is required by firmware\n(OPAL), to know size of memory to allocate to capture CPU state, in the\nevent of a crash\n\nReviewed-by: Hari Bathini \nReviewed-by: Sourabh Jain \nSigned-off-by: Aditya Gupta \n---\n hw/ppc/pnv.c | 25 +++++++++++++++++++++++++\n 1 file changed, 25 insertions(+)","diff":"diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 524563dcfc23..09b69c355a45 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -748,10 +748,35 @@ static void pnv_powerdown_notify(Notifier *n, void *opaque)\n \n static void pnv_reset(MachineState *machine, ResetType type)\n {\n+ PnvMachineState *pnv = PNV_MACHINE(machine);\n void *fdt;\n \n qemu_devices_reset(type);\n \n+ if (!pnv->mpipl_state.is_next_boot_mpipl) {\n+ /*\n+ * Set the \"Thread Register State Entry Size\", so that firmware can\n+ * allocate enough memory to capture CPU state in the event of a\n+ * crash\n+ */\n+\n+ MpiplProcDumpArea proc_area;\n+\n+ proc_area.version = PROC_DUMP_AREA_VERSION_P9;\n+ proc_area.thread_size = cpu_to_be32(sizeof(MpiplPreservedCPUState));\n+\n+ /* These are to be allocated & assigned by the firmware */\n+ proc_area.alloc_addr = 0;\n+ proc_area.alloc_size = 0;\n+\n+ /* These get assigned after crash, when QEMU preserves the registers */\n+ proc_area.dest_addr = 0;\n+ proc_area.act_size = 0;\n+\n+ cpu_physical_memory_write(PROC_DUMP_AREA_OFF, &proc_area,\n+ sizeof(proc_area));\n+ }\n+\n fdt = machine->fdt;\n cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));\n }\n","prefixes":["v6","06/10"]}