{"id":2227757,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227757/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-4-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1777017460-243543-4-git-send-email-shawn.lin@rock-chips.com>","date":"2026-04-24T07:57:36","name":"[v4,3/7] PCI/MSI: Introduce __pcim_enable_msi_range()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"763e112f3b52ada095aa003bb3c80e13b6f4a5df","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/1.1/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-4-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":501313,"url":"http://patchwork.ozlabs.org/api/1.1/series/501313/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501313","date":"2026-04-24T07:57:33","name":"Add Devres managed IRQ vectors allocation","version":4,"mbox":"http://patchwork.ozlabs.org/series/501313/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227757/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227757/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=QxiWhGir;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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arc=none smtp.client-ip=117.135.214.68","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[PATCH v4 3/7] PCI/MSI: Introduce __pcim_enable_msi_range()","Date":"Fri, 24 Apr 2026 15:57:36 +0800","Message-Id":"<1777017460-243543-4-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","References":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","X-HM-Tid":"0a9dbe7f5b7009cckunm66d640875eac0","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlCTk5OVkgYS0MZGh1CTkpOSlYVFA\n\tkWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU\n\t9PT0tVSktLVUtZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=QxiWhGir9DGlbp2RTIJMDv/yPic3147goPsX4DLiBwxs1MIG5oBX5R1B4d4szHHOlg0kT7VGEeb/sKEWJK0fokPQZriBfvybLkFv1AdmX+qfFMpvcrFhckfG9lwethhK/Ys7hp1ldaAXFtlhFaQ8IBF6BZS7uaf4GawAjUzPkiQ=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=Gxg7934kII0Uyamt7yOZlWU8O9tnaRuI4ujeJUpRmZE=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"Introduce __pcim_enable_msi_range(), a devres-managed variant of\n__pci_enable_msi_range(). The new function provides automatic cleanup\nof MSI interrupts via devres, reducing the risk of resource leaks and\nsimplifying driver error handling.\n\nThis function is particularly useful for drivers that already use\npcim_enable_device() and want consistent devres management for all\nPCI resources, including MSI interrupts.\n\nDrivers can replace calls to __pci_enable_msi_range() with\n__pcim_enable_msi_range() to benefit from automatic cleanup without\nchanging their core logic.\n\nSigned-off-by: Shawn Lin \n---\n\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n drivers/pci/msi/msi.c | 20 ++++++++++++++++++++\n drivers/pci/msi/msi.h | 1 +\n 2 files changed, 21 insertions(+)","diff":"diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c\nindex 5c196c2..0aaff57 100644\n--- a/drivers/pci/msi/msi.c\n+++ b/drivers/pci/msi/msi.c\n@@ -499,6 +499,26 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n \treturn pci_msi_range_init(dev, minvec, maxvec, nvec, affd);\n }\n \n+int __pcim_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n+\t\t\t struct irq_affinity *affd)\n+{\n+\tint nvec, rc;\n+\n+\tnvec = pci_msi_range_alloc(dev, minvec, maxvec);\n+\tif (nvec < 0)\n+\t\treturn nvec;\n+\n+\trc = msi_setup_device_data(&dev->dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = devm_add_action(&dev->dev, pcim_msi_release, dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn pci_msi_range_init(dev, minvec, maxvec, nvec, affd);\n+}\n+\n /**\n * pci_msi_vec_count - Return the number of MSI vectors a device can send\n * @dev: device to report about\ndiff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h\nindex 0b420b3..81c6b099 100644\n--- a/drivers/pci/msi/msi.h\n+++ b/drivers/pci/msi/msi.h\n@@ -94,6 +94,7 @@ void pci_msi_shutdown(struct pci_dev *dev);\n void pci_msix_shutdown(struct pci_dev *dev);\n void pci_free_msi_irqs(struct pci_dev *dev);\n int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd);\n+int __pcim_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd);\n int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n \t\t\t int maxvec, struct irq_affinity *affd, int flags);\n void __pci_restore_msi_state(struct pci_dev *dev);\n","prefixes":["v4","3/7"]}