{"id":2227756,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227756/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com>","date":"2026-04-24T07:57:37","name":"[v4,4/7] PCI/MSI: Introduce __pcim_enable_msix_range()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a549d7aef8bd9d45a7ebc9cf37ce402397aa2feb","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/1.1/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":501313,"url":"http://patchwork.ozlabs.org/api/1.1/series/501313/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501313","date":"2026-04-24T07:57:33","name":"Add Devres managed IRQ vectors allocation","version":4,"mbox":"http://patchwork.ozlabs.org/series/501313/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227756/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227756/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=kV+ImfAB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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arc=none smtp.client-ip=117.135.214.68","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[PATCH v4 4/7] PCI/MSI: Introduce __pcim_enable_msix_range()","Date":"Fri, 24 Apr 2026 15:57:37 +0800","Message-Id":"<1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","References":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","X-HM-Tid":"0a9dbe7fb4aa09cckunm66d640875eb88","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlCTUgZVkpMSkgdTRpLSkNNSlYVFA\n\tkWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU\n\t9PT0tVSktLVUtZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=kV+ImfABC4r83H00yEIwQYw9ay6IYjhyT4tdOY1E74JcBwMONHI8S6gqUOMRNEFaXfjVYeedD9OWdTLVDBhym6jj1dV3j2GQDampBipoWhgckyi9DG3YNpMMpnWKp5ABmM5S6WQIZnzIPpU1dCbFeKLFIPZ/j19xeF8ZambYmbI=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=tUGBWeaNM4DC0fKMSuIkB31wERPflv0/PrY+shHbQpg=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"Introduce __pcim_enable_msix_range(), a devres-managed variant of\n__pci_enable_msix_range(). Similar to the previously added MSI variant,\nthis function provides automatic cleanup of MSI-X interrupts via devres,\nreducing the risk of resource leaks and simplifying driver error handling.\n\nThis function is particularly useful for drivers that already use\npcim_enable_device() and want consistent devres management for all\nPCI resources, including MSI-X interrupts.\n\nDrivers can replace calls to __pci_enable_msix_range() with\n__pcim_enable_msix_range() to benefit from automatic cleanup without\nchanging their core logic. The flags parameter (e.g., PCI_IRQ_VIRTUAL)\nis fully supported and passed through to the underlying functions.\n\nThis completes the set of devres-managed MSI/MSI-X allocation functions,\nproviding a consistent API for driver authors who prefer automatic\nresource management.\n\nSigned-off-by: Shawn Lin \n---\n\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n drivers/pci/msi/msi.c | 22 ++++++++++++++++++++++\n drivers/pci/msi/msi.h | 2 ++\n 2 files changed, 24 insertions(+)","diff":"diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c\nindex 0aaff57..8fdf40d 100644\n--- a/drivers/pci/msi/msi.c\n+++ b/drivers/pci/msi/msi.c\n@@ -930,6 +930,28 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,\n \treturn pci_msix_range_init(dev, entries, minvec, nvec, hwsize, affd);\n }\n \n+int __pcim_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,\n+\t\t\t int minvec, int maxvec, struct irq_affinity *affd,\n+\t\t\t int flags)\n+{\n+\tint hwsize, nvec, rc;\n+\n+\thwsize = pci_msix_range_alloc(dev, entries, minvec,\n+\t\t\t\t maxvec, flags, &nvec);\n+\tif (hwsize < 0)\n+\t\treturn hwsize;\n+\n+\trc = msi_setup_device_data(&dev->dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = devm_add_action(&dev->dev, pcim_msi_release, dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn pci_msix_range_init(dev, entries, minvec, nvec, hwsize, affd);\n+}\n+\n void __pci_restore_msix_state(struct pci_dev *dev)\n {\n \tstruct msi_desc *entry;\ndiff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h\nindex 81c6b099..e6364a8 100644\n--- a/drivers/pci/msi/msi.h\n+++ b/drivers/pci/msi/msi.h\n@@ -97,6 +97,8 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct i\n int __pcim_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd);\n int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n \t\t\t int maxvec, struct irq_affinity *affd, int flags);\n+int __pcim_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n+\t\t\t int maxvec, struct irq_affinity *affd, int flags);\n void __pci_restore_msi_state(struct pci_dev *dev);\n void __pci_restore_msix_state(struct pci_dev *dev);\n \n","prefixes":["v4","4/7"]}