{"id":2227755,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227755/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-2-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1777017460-243543-2-git-send-email-shawn.lin@rock-chips.com>","date":"2026-04-24T07:57:34","name":"[v4,1/7] PCI/MSI: Split __pci_enable_msi_range() for reuse","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"16e1ffe6d2694a3405764a484ddf945dd3ac8b53","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/1.1/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-2-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":501313,"url":"http://patchwork.ozlabs.org/api/1.1/series/501313/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501313","date":"2026-04-24T07:57:33","name":"Add Devres managed IRQ vectors allocation","version":4,"mbox":"http://patchwork.ozlabs.org/series/501313/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227755/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227755/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=CzhALnD4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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t=1777018416; c=relaxed/simple;\n\tbh=ucvoA6m7JfR3Nj1G2YOXMjpfqrdrg7M+xGv0L82Qp+0=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References;\n b=iYCJapfipY95dCO6s7+8HZnPQ39QfEx6mry/WKIWskQYGgwIK4Egbk8sxE+62u3RAHp0eLz7TvWlPwX77OoI4sZMqiVvK/DOBD9GgeS0EEU9BaolzPAt7n+rD6wPivC9XhKqGftF8trNayAFJui5OJft0/xQG2YLZq832sHK9NQ=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=CzhALnD4; arc=none smtp.client-ip=45.254.49.231","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[PATCH v4 1/7] PCI/MSI: Split __pci_enable_msi_range() for reuse","Date":"Fri, 24 Apr 2026 15:57:34 +0800","Message-Id":"<1777017460-243543-2-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","References":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","X-HM-Tid":"0a9dbe7eed5a09cckunm66d640875e99d","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaSElIVhodGElIGU0ZS0JJHVYVFA\n\tkWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU\n\t9PT0hVSktLVUpCS0tZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=CzhALnD46OEmNETyysSV2GQ+TmL3gdEGwFu2vbxv2epSuzPPf1FQnfqmo4CWpblBZkrgzCVuVkSFM5Snc9rWL4vZzxlmFp7UoXUP0THFGfU5FoU3CpRWRNhRJ4mqV5FSvemRO611fDfSFkxRYn2Gt6XXziJY6pREw1yMD+pYKnQ=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=nIkwOBEeQfi7KPrZZjVS6eHLn6sWpJbd//REZco0tWk=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"Splits the __pci_enable_msi_range() function into two helper\nfunctions without changing the original behavior. The purpose is to allow\nfuture functions (particularly managed devres variants) to reuse these\ncomponents.\n\nThe split is as follows:\n\n1. pci_msi_range_alloc(): Handles the allocation logic, including\n parameter validation and vector number calculation. This function returns\n the calculated number of vectors or an error code.\n\n2. pci_msi_range_init(): Handles the initialization of MSI context\n and the actual MSI capability setup. This function takes the pre-calculated\n number of vectors as input.\n\n3. The original __pci_enable_msi_range() is now a wrapper that calls these\n two helper functions in sequence, maintaining exact same behavior.\n\nThis is a preparatory step for introducing devres-managed MSI allocation\nAPI that will share the allocation logic while providing automatic cleanup\nvia devres.\n\nNo functional changes intended.\n\nSigned-off-by: Shawn Lin \n---\n\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n drivers/pci/msi/msi.c | 30 ++++++++++++++++++++++++------\n 1 file changed, 24 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c\nindex 81d24a2..748dba6 100644\n--- a/drivers/pci/msi/msi.c\n+++ b/drivers/pci/msi/msi.c\n@@ -420,11 +420,9 @@ static int msi_capability_init(struct pci_dev *dev, int nvec,\n \treturn __msi_capability_init(dev, nvec, masks);\n }\n \n-int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n-\t\t\t struct irq_affinity *affd)\n+static int pci_msi_range_alloc(struct pci_dev *dev, int minvec, int maxvec)\n {\n \tint nvec;\n-\tint rc;\n \n \tif (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)\n \t\treturn -EINVAL;\n@@ -451,9 +449,13 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n \tif (nvec < minvec)\n \t\treturn -ENOSPC;\n \n-\trc = pci_setup_msi_context(dev);\n-\tif (rc)\n-\t\treturn rc;\n+\treturn nvec;\n+}\n+\n+static int pci_msi_range_init(struct pci_dev *dev, int minvec, int maxvec,\n+\t\t\t int nvec, struct irq_affinity *affd)\n+{\n+\tint rc;\n \n \tif (!pci_setup_msi_device_domain(dev, nvec))\n \t\treturn -ENODEV;\n@@ -481,6 +483,22 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n \t}\n }\n \n+int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,\n+\t\t\t struct irq_affinity *affd)\n+{\n+\tint nvec, rc;\n+\n+\tnvec = pci_msi_range_alloc(dev, minvec, maxvec);\n+\tif (nvec < 0)\n+\t\treturn nvec;\n+\n+\trc = pci_setup_msi_context(dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn pci_msi_range_init(dev, minvec, maxvec, nvec, affd);\n+}\n+\n /**\n * pci_msi_vec_count - Return the number of MSI vectors a device can send\n * @dev: device to report about\n","prefixes":["v4","1/7"]}