{"id":2227754,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227754/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424080508.53992-14-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424080508.53992-14-jamin_lin@aspeedtech.com>","date":"2026-04-24T08:05:27","name":"[v5,13/18] hw/usb/hcd-ehci: Implement 64-bit iTD descriptor addressing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7ce861f2cd09dd441115df05e92d36a5a9b11873","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/1.1/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424080508.53992-14-jamin_lin@aspeedtech.com/mbox/","series":[{"id":501315,"url":"http://patchwork.ozlabs.org/api/1.1/series/501315/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501315","date":"2026-04-24T08:05:08","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":5,"mbox":"http://patchwork.ozlabs.org/series/501315/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227754/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227754/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=UFjn81Zz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" , Laurent Vivier ,\n Nicholas Piggin ,\n Harsh Prateek Bora ,\n Halil Pasic ,\n Christian Borntraeger ,\n Eric Farman , Matthew Rosato ,\n Ilya Leoshkevich , David Hildenbrand ,\n Cornelia Huck ,\n \"open list:ASPEED BMCs\" ,\n \"open list:All patches CC here\" ,\n \"open list:sPAPR pseries\" ,\n \"open list:S390 Virtio-ccw\" ","CC":"Jamin Lin , Troy Lee ,\n \"farosas@suse.de\" , \"flwu@google.com\" ,\n \"nabihestefan@google.com\" ","Subject":"[PATCH v5 13/18] hw/usb/hcd-ehci: Implement 64-bit iTD descriptor\n addressing","Thread-Topic":"[PATCH v5 13/18] hw/usb/hcd-ehci: Implement 64-bit iTD\n descriptor addressing","Thread-Index":"AQHc08EcF0LpWa9940qoIDvEhKbrDg==","Date":"Fri, 24 Apr 2026 08:05:27 +0000","Message-ID":"<20260424080508.53992-14-jamin_lin@aspeedtech.com>","References":"<20260424080508.53992-1-jamin_lin@aspeedtech.com>","In-Reply-To":"<20260424080508.53992-1-jamin_lin@aspeedtech.com>","Accept-Language":"zh-TW, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=UFjn81Zz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-Exchange-RoutingPolicyChecked":"\n hoZ699vrHd64UxKaRPkEqYKgInxNfqI82VivjpqmT+JdNk9FP67kN1lgeSpB8YLMuJq0Z1vWGsUT+QNOkKUo2BqNGjtkP+cuOKVui1Y/4qip5jubEjQqD6rdfAIu92LmFVv7TGjS2THcNwZg+0yAEKEIcsHGIYiqbob1kYEFtexV7o1l0sWjoFPvMMw3i+121LXTS/ZKJWclOGRrGdbfG60vg58OcJ1tN3oJnAKSrtrvEOoIhow83GL4UykmWst1u1gOI0/IeYH/VA/09w1OAvlPWjtKZbFcxkLT2ZEBgN6hWzTbwNMl279ZZmv/pq6BKdRnkDlZNLxgO9rdsO80jw==","X-OriginatorOrg":"aspeedtech.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"TYPPR06MB8206.apcprd06.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n ea9ca9df-e575-4842-134a-08dea1d83ecd","X-MS-Exchange-CrossTenant-originalarrivaltime":"24 Apr 2026 08:05:27.1585 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43d4aa98-e35b-4575-8939-080e90d5a249","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n /pyUCQHypZdAp/9MXOR9TxuJSWGtcy8Z8LwCdqV5EHh/aJQNfX9ZwzgTwNaR1bXTU9fKClf8J3p54utOMuIGfdsyT10s3F2iUAynUeKe8+g=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SEZPR06MB5856","Received-SPF":"pass client-ip=2a01:111:f403:c405::7;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=TYDPR03CU002.outbound.protection.outlook.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"EHCI supports 64-bit control data structure addressing when the\n64-bit Addressing Capability bit in HCCPARAMS is set. In that mode,\nthe CTRLDSSEGMENT register provides the upper 32 bits that are\nconcatenated with 32-bit link pointer values to form full 64-bit\ndescriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n\niTD link pointers are stored as 32-bit values and must be expanded\nto full 64-bit descriptor addresses when 64-bit mode is enabled.\nUpdate the iTD traversal path to use ehci_get_desc_addr() when\nfollowing link pointers.\n\nAppendix B also defines high dword fields for iTD buffer pointers.\nAdd bufptr_hi[7] to EHCIitd and use ehci_get_buf_addr() to construct\nfull 64-bit buffer addresses from bufptr[] and bufptr_hi[] fields\nwhen processing isochronous transfers. This allows buffers above\n4GB to be handled correctly.\n\nWhen 64-bit capability is disabled, descriptor and buffer addresses\nremain 32-bit and existing behaviour is unchanged.\n\nSigned-off-by: Jamin Lin \nReviewed-by: Philippe Mathieu-Daudé \n---\n hw/usb/hcd-ehci.h | 1 +\n hw/usb/hcd-ehci.c | 9 ++++++---\n 2 files changed, 7 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\nindex fc66aacd9f..8e6a8cdfb0 100644\n--- a/hw/usb/hcd-ehci.h\n+++ b/hw/usb/hcd-ehci.h\n@@ -63,6 +63,7 @@ typedef struct EHCIitd {\n #define ITD_BUFPTR_MAXPKT_SH 0\n #define ITD_BUFPTR_MULT_MASK 0x00000003\n #define ITD_BUFPTR_MULT_SH 0\n+ uint32_t bufptr_hi[7];\n } EHCIitd;\n \n /*\ndiff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\nindex e82e0f625c..43a01a796f 100644\n--- a/hw/usb/hcd-ehci.c\n+++ b/hw/usb/hcd-ehci.c\n@@ -1464,7 +1464,8 @@ static int ehci_process_itd(EHCIState *ehci,\n return -1;\n }\n \n- ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);\n+ ptr1 = ehci_get_buf_addr(ehci, itd->bufptr_hi[pg],\n+ itd->bufptr[pg], ITD_BUFPTR_MASK);\n qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as);\n if (off + len > 4096) {\n /* transfer crosses page border */\n@@ -1472,7 +1473,9 @@ static int ehci_process_itd(EHCIState *ehci,\n qemu_sglist_destroy(&ehci->isgl);\n return -1; /* avoid page pg + 1 */\n }\n- ptr2 = (itd->bufptr[pg + 1] & ITD_BUFPTR_MASK);\n+ ptr2 = ehci_get_buf_addr(ehci, itd->bufptr_hi[pg + 1],\n+ itd->bufptr[pg + 1],\n+ ITD_BUFPTR_MASK);\n uint32_t len2 = off + len - 4096;\n uint32_t len1 = len - len2;\n qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);\n@@ -1762,7 +1765,7 @@ static int ehci_state_fetchitd(EHCIState *ehci, int async)\n \n put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,\n sizeof(EHCIitd) >> 2);\n- ehci_set_fetch_addr(ehci, async, itd.next);\n+ ehci_set_fetch_addr(ehci, async, ehci_get_desc_addr(ehci, itd.next));\n ehci_set_state(ehci, async, EST_FETCHENTRY);\n \n return 1;\n","prefixes":["v5","13/18"]}