{"id":2227735,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227735/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-3-git-send-email-shawn.lin@rock-chips.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1777017460-243543-3-git-send-email-shawn.lin@rock-chips.com>","date":"2026-04-24T07:57:35","name":"[v4,2/7] PCI/MSI: Split __pci_enable_msix_range() for reuse","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"768c61670b465479dc5a115343aeeef1671f3f1f","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/1.1/people/66993/?format=json","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-3-git-send-email-shawn.lin@rock-chips.com/mbox/","series":[{"id":501313,"url":"http://patchwork.ozlabs.org/api/1.1/series/501313/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501313","date":"2026-04-24T07:57:33","name":"Add Devres managed IRQ vectors allocation","version":4,"mbox":"http://patchwork.ozlabs.org/series/501313/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227735/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227735/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=AhwRyhHn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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arc=none smtp.client-ip=220.197.31.76","From":"Shawn Lin ","To":"Bjorn Helgaas ","Cc":"Nirmal Patel ,\n\tJonathan Derrick ,\n\tKurt Schwemmer ,\n\tLogan Gunthorpe ,\n\tPhilipp Stanner ,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin ","Subject":"[PATCH v4 2/7] PCI/MSI: Split __pci_enable_msix_range() for reuse","Date":"Fri, 24 Apr 2026 15:57:35 +0800","Message-Id":"<1777017460-243543-3-git-send-email-shawn.lin@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","References":"<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>","X-HM-Tid":"0a9dbe7f1fe909cckunm66d640875ea13","X-HM-MType":"1","X-HM-Spam-Status":"e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkZQxhOVh5ISk8eTB1OTU4eQlYVFA\n\tkWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU\n\t9PT0tVSktLVUtZBg++","DKIM-Signature":"a=rsa-sha256;\n\tb=AhwRyhHnj9DsjTDh67DyDvlCs+z03o1+UP6yPcYihmMs3BpAdAi1U3pkBaQOU8AyPADAoRs2YEI3Fit9RUFgApvI38kpG7vFmoWyUwCv9IwHWNnJt7FCRe6RgjorYz5YaaQOIgEdy0Bg+O6BDwQfAK0fzandnYewo/9WsNlufmw=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=7kjOoOEShdho0LvaXR4AZ8l8XbTuFKa4ZTPV+311oNE=;\n\th=date:mime-version:subject:message-id:from;","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""},"content":"Splits the __pci_enable_msix_range() function into two helper\nfunctions without changing the original behavior. The purpose is to allow\nfuture functions (particularly managed devres variants) to reuse these\ncomponents.\n\nThe split is as follows:\n\n1. pci_msix_range_alloc(): Handles the allocation logic, including\n parameter validation, hardware vector count verification, and entry\n validation. This function calculates the actual number of vectors\n to allocate and returns the hardware-supported vector count.\n\n2. pci_msix_range_init(): Handles the initialization of MSI-X context\n and the actual MSI-X capability setup. This function takes the\n pre-determined number of vectors and hardware vector count as inputs.\n\n3. The original __pci_enable_msix_range() is now a wrapper that calls\n these two helper functions in sequence, maintaining exact same\n behavior.\n\nThis is a preparatory step for introducing devres-managed MSI-X allocation\nAPI that will share the allocation logic while providing automatic cleanup\nvia devres.\n\nNo functional changes intended.\n\nSigned-off-by: Shawn Lin \n---\n\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n drivers/pci/msi/msi.c | 38 ++++++++++++++++++++++++++++++--------\n 1 file changed, 30 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c\nindex 748dba6..5c196c2 100644\n--- a/drivers/pci/msi/msi.c\n+++ b/drivers/pci/msi/msi.c\n@@ -820,10 +820,10 @@ static bool pci_msix_validate_entries(struct pci_dev *dev, struct msix_entry *en\n \treturn true;\n }\n \n-int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n-\t\t\t int maxvec, struct irq_affinity *affd, int flags)\n+static int pci_msix_range_alloc(struct pci_dev *dev, struct msix_entry *entries,\n+\t\t\t\tint minvec, int maxvec, int flags, int *nvec_ret)\n {\n-\tint hwsize, rc, nvec = maxvec;\n+\tint hwsize, nvec = maxvec;\n \n \tif (maxvec < minvec)\n \t\treturn -ERANGE;\n@@ -858,12 +858,16 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int\n \t\t\tnvec = hwsize;\n \t}\n \n-\tif (nvec < minvec)\n-\t\treturn -ENOSPC;\n+\t*nvec_ret = nvec;\n \n-\trc = pci_setup_msi_context(dev);\n-\tif (rc)\n-\t\treturn rc;\n+\treturn hwsize;\n+}\n+\n+static int pci_msix_range_init(struct pci_dev *dev, struct msix_entry *entries,\n+\t\t\t int minvec, int nvec, int hwsize,\n+\t\t\t struct irq_affinity *affd)\n+{\n+\tint rc;\n \n \tif (!pci_setup_msix_device_domain(dev, hwsize))\n \t\treturn -ENODEV;\n@@ -888,6 +892,24 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int\n \t}\n }\n \n+int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,\n+\t\t\t int minvec, int maxvec, struct irq_affinity *affd,\n+\t\t\t int flags)\n+{\n+\tint hwsize, nvec, rc;\n+\n+\thwsize = pci_msix_range_alloc(dev, entries, minvec,\n+\t\t\t\t maxvec, flags, &nvec);\n+\tif (hwsize < 0)\n+\t\treturn hwsize;\n+\n+\trc = pci_setup_msi_context(dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn pci_msix_range_init(dev, entries, minvec, nvec, hwsize, affd);\n+}\n+\n void __pci_restore_msix_state(struct pci_dev *dev)\n {\n \tstruct msi_desc *entry;\n","prefixes":["v4","2/7"]}