{"id":2227719,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227719/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com>","date":"2026-04-24T06:31:24","name":"pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchip","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7d06587a35372c5267dab7a4f163bdb41eb5f746","submitter":{"id":93246,"url":"http://patchwork.ozlabs.org/api/1.1/people/93246/?format=json","name":"Sneh Mankad","email":"sneh.mankad@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com/mbox/","series":[{"id":501309,"url":"http://patchwork.ozlabs.org/api/1.1/series/501309/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501309","date":"2026-04-24T06:31:24","name":"pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchip","version":1,"mbox":"http://patchwork.ozlabs.org/series/501309/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227719/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227719/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Hqk6LNcp;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Coo32nJ+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com>","X-B4-Tracking":"v=1; b=H4sIADsO62kC/x3MQQqAIBBA0avErBPKJKirRITYWANhNiMRhHdPW\n r7F/y8IMqHAWL3AeJPQGQraugK327ChorUYdKP7xmijIgWX+FiIL7dTXCTZhKKsReM77QffI5Q\n 4Mnp6/vE05/wB4xH6RmgAAAA=","X-Change-ID":"20260424-pinctrl_irqchip_states-aae4f32f9f6e","To":"Bjorn Andersson , Linus Walleij ","Cc":"linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n linux-kernel@vger.kernel.org,\n Maulik Shah ,\n Sneh Mankad ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777012300; l=2906;\n i=sneh.mankad@oss.qualcomm.com; s=20250818; h=from:subject:message-id;\n bh=h02fdp0DbXznNzmrHM3xZOzhwlTmloFlpI4uxtWczsU=;\n b=oitZkZ74zfH3TPM1mCDzF2vNaNn8TpgKaiEjNAuNXb/buNd9xf0VDxS4p13BmJNTfE6nbvE0e\n +HYXjwfB9/QA6iMdq3ILBwl1pnoKSjJ7RcMFuvNuy+abMSNZ722qYQk","X-Developer-Key":"i=sneh.mankad@oss.qualcomm.com; a=ed25519;\n pk=sv57EGwdcfnp6xJmoBCIT1JFSqWI+gawRHkJWj/T2B0=","X-Proofpoint-ORIG-GUID":"V_47yJ5IHdin019bbsIby9NXU83TWjKg","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI0MDA1OCBTYWx0ZWRfX7Ajl3W4zcd0i\n qaX1Umzigkf0fKYq5IzlSkhqD6H3SU4TB0c2xT+u/WDRMVI4drDozo/6m/olfbGUP0tNBOMcy87\n DDU9H6cPEdCtoiMbsXqIrcTNro3x6NbuQQ/enPbNrqeRVcLZPO3fe3rqSGi7euA+/VvqXiejNfX\n 6D6YQAZhx0plEXHoT97bICURF3Jo88QlVwLoFUib/YNONfTAcecdbWPievN4+h0IQ/1meU6Y1AG\n VsVQ5UcEfiPQkS+M4sfx0Ihuc/eZgKxz+0Xi0RK/QiDyRREA8us8lwz3O/iRHPVMyDdpthPzYiZ\n dqMB1fHAvleEUSCQuZy938ST8uBZgUWWRRAM2eYmJEBYQARBNjr5bVrP32AItfa6Ee6KjXFvA7d\n gAHIL6QQJgG5AOzT6HUrvZO/4SXhX1GE8xU8KFwkW/D7PhqTTcap0ZHK/TfOu0edFo3hqf6On7s\n 9E9LHEEPJszqzsp0oOg==","X-Authority-Analysis":"v=2.4 cv=fP4JG5ae c=1 sm=1 tr=0 ts=69eb0e51 cx=c_pps\n a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22\n a=EUspDBNiAAAA:8 a=V_Y7YcmqozLAU5NnLsYA:9 a=QEXdDO2ut3YA:10\n a=_Vgx9l1VpLgwpw_dHYaR:22","X-Proofpoint-GUID":"V_47yJ5IHdin019bbsIby9NXU83TWjKg","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 clxscore=1011 priorityscore=1501 adultscore=0 suspectscore=0\n impostorscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240058"},"content":"From: Maulik Shah \n\nMPM irqchip monitors the interrupts during SoC sleep state and after wakeup\nreplays the edge interrupt by making it pending at respective irqchip by\ninvoking irq_set_irqchip_state() API. The msm gpio irqchip however do not\nimplement this function making it impossible to replay the gpio interrupt\non any MPM irqchip based SoC.\n\nAdd the missing irq_get/set_irqchip_state() APIs. Implement only\nIRQCHIP_STATE_PENDING case which MPM irqchip uses.\n\nSigned-off-by: Maulik Shah \nSigned-off-by: Sneh Mankad \n---\n drivers/pinctrl/qcom/pinctrl-msm.c | 39 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 39 insertions(+)\n\n\n---\nbase-commit: b4e07588e743c989499ca24d49e752c074924a9a\nchange-id: 20260424-pinctrl_irqchip_states-aae4f32f9f6e\n\nBest regards,","diff":"diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\nindex 45b3a2763eb85405fecdd4770ba3d4ab684563f0..925fca82252413d8e21fb47a0cc3a9ade7d5fe67 100644\n--- a/drivers/pinctrl/qcom/pinctrl-msm.c\n+++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n@@ -1305,6 +1305,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d,\n \treturn -EINVAL;\n }\n \n+static int msm_gpio_irq_set_irqchip_state(struct irq_data *d,\n+\t\t\t\t\t enum irqchip_irq_state which, bool val)\n+{\n+\tstruct gpio_chip *gc = irq_data_get_irq_chip_data(d);\n+\tstruct msm_pinctrl *pctrl = gpiochip_get_data(gc);\n+\tconst struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];\n+\n+\tif (which != IRQCHIP_STATE_PENDING)\n+\t\treturn -EINVAL;\n+\n+\tif (test_bit(d->hwirq, pctrl->skip_wake_irqs))\n+\t\treturn -EINVAL;\n+\n+\tmsm_writel_intr_status(val, pctrl, g);\n+\n+\treturn 0;\n+}\n+\n+static int msm_gpio_irq_get_irqchip_state(struct irq_data *d,\n+\t\t\t\t\t enum irqchip_irq_state which, bool *val)\n+{\n+\tstruct gpio_chip *gc = irq_data_get_irq_chip_data(d);\n+\tstruct msm_pinctrl *pctrl = gpiochip_get_data(gc);\n+\tconst struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];\n+\n+\tif (which != IRQCHIP_STATE_PENDING)\n+\t\treturn -EINVAL;\n+\n+\tif (test_bit(d->hwirq, pctrl->skip_wake_irqs))\n+\t\treturn -EINVAL;\n+\n+\tg = &pctrl->soc->groups[d->hwirq];\n+\t*val = msm_readl_intr_status(pctrl, g);\n+\n+\treturn 0;\n+}\n+\n static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)\n {\n \tstruct gpio_chip *gc = irq_data_get_irq_chip_data(d);\n@@ -1393,6 +1430,8 @@ static const struct irq_chip msm_gpio_irq_chip = {\n \t.irq_request_resources\t= msm_gpio_irq_reqres,\n \t.irq_release_resources\t= msm_gpio_irq_relres,\n \t.irq_set_affinity\t= msm_gpio_irq_set_affinity,\n+\t.irq_set_irqchip_state = msm_gpio_irq_set_irqchip_state,\n+\t.irq_get_irqchip_state = msm_gpio_irq_get_irqchip_state,\n \t.irq_set_vcpu_affinity\t= msm_gpio_irq_set_vcpu_affinity,\n \t.flags\t\t\t= (IRQCHIP_MASK_ON_SUSPEND |\n \t\t\t\t IRQCHIP_SET_TYPE_MASKED |\n","prefixes":[]}