{"id":2227699,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227699/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424050509.3935180-2-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424050509.3935180-2-frank.chang@sifive.com>","date":"2026-04-24T05:05:08","name":"[v4,1/2] target/riscv: Update MISA.C for Zc* extensions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d0a373264e66ea0f4085d00e0c4981e9630f7eeb","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/1.1/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424050509.3935180-2-frank.chang@sifive.com/mbox/","series":[{"id":501301,"url":"http://patchwork.ozlabs.org/api/1.1/series/501301/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501301","date":"2026-04-24T05:05:08","name":"Set MISA.[C|X] based on the selected extensions","version":4,"mbox":"http://patchwork.ozlabs.org/series/501301/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227699/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227699/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=koBfIg+C;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x433.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nMISA.C is set if the following extensions are selected:\n * Zca and not F.\n * Zca, Zcf and F (but not D) is specified (RV32 only).\n * Zca, Zcf and Zcd if D is specified (RV32 only).\n * Zca, Zcd if D is specified (RV64 only).\n\nTherefore, MISA.C must be set according to the Zc* extension rules.\n\nWarn the user if RVC is explicitly disabled but MISA.C is required by\nthe rules above.\n\nSigned-off-by: Frank Chang \nReviewed-by: Max Chou \n---\n target/riscv/tcg/tcg-cpu.c | 39 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 39 insertions(+)","diff":"diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f78088956..5db166c01e9 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -1163,6 +1163,44 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)\n }\n }\n \n+/*\n+ * MISA.C is set if the following extensions are selected:\n+ * - Zca and not F.\n+ * - Zca, Zcf and F (but not D) is specified on RV32.\n+ * - Zca, Zcf and Zcd if D is specified on RV32.\n+ * - Zca, Zcd if D is specified on RV64.\n+ */\n+static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n+{\n+ CPURISCVState *env = &cpu->env;\n+ bool set_misa_c = false;\n+\n+ if (riscv_has_ext(env, RVC)) {\n+ return;\n+ }\n+\n+ if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) {\n+ set_misa_c = true;\n+ } else if (riscv_cpu_mxl(env) == MXL_RV32 &&\n+ cpu->cfg.ext_zca && cpu->cfg.ext_zcf &&\n+ (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd :\n+ riscv_has_ext(env, RVF))) {\n+ set_misa_c = true;\n+ } else if (riscv_cpu_mxl(env) == MXL_RV64 &&\n+ cpu->cfg.ext_zca && cpu->cfg.ext_zcd) {\n+ set_misa_c = true;\n+ }\n+\n+ if (set_misa_c) {\n+ if (cpu_misa_ext_is_user_set(RVC)) {\n+ warn_report(\"RVC mandated by Zca/Zcf/Zcd extensions\");\n+ return;\n+ }\n+\n+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVC);\n+ }\n+}\n+\n void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n {\n CPURISCVState *env = &cpu->env;\n@@ -1170,6 +1208,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n \n riscv_cpu_init_implied_exts_rules();\n riscv_cpu_enable_implied_rules(cpu);\n+ riscv_cpu_update_misa_c(cpu);\n \n riscv_cpu_validate_misa_priv(env, &local_err);\n if (local_err != NULL) {\n","prefixes":["v4","1/2"]}