{"id":2227682,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227682/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-5-richard.henderson@linaro.org>","date":"2026-04-24T04:29:38","name":"[v2,04/40] target/arm: Implement FEAT_FAMINMAX for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bbbf0f9c1511fd920eebb8bcb990f1b360e2dda0","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-5-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227682/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227682/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=XWd1AnBm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20VP33Ptz1yDD\n\tfor ; Fri, 24 Apr 2026 14:34:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Bm-0005mF-Up; Fri, 24 Apr 2026 00:30:50 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Bl-0005j9-I2\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:49 -0400","from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Bi-0002YG-KQ\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:49 -0400","by mail-oa1-x2b.google.com with SMTP id\n 586e51a60fabf-42321c8b8f5so6146911fac.1\n for ; Thu, 23 Apr 2026 21:30:44 -0700 (PDT)","from stoup.. ([172.58.183.19]) by smtp.gmail.com with ESMTPSA id\n 586e51a60fabf-42b9ac54ec5sm18880864fac.13.2026.04.23.21.30.38\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 23 Apr 2026 21:30:40 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777005042; x=1777609842; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=o688HWl5XrNHYPI7Z2Xn/6ecck2Zhe/qTWuxAA2gZDk=;\n b=XWd1AnBmJqCVi8SEC8u4S+wcD9JGEuUpXBAwzab2XjGsnIhXhZTydaULzBVwGjhPaI\n p6PBF/CDjFVLTm3VFOMm28jXsHERCVV+tMv+ECTpd5/owKWzoMhzxPOGXdPhFDNCRHKl\n eKHIdxvVnQVJkBKbBLD5s0YQctrvCAUmZfEIAoM+i3pzAOr4Rlnsid3gO8AvtTOrWEG8\n ShseKZjtFwd9M56jP5t98YOw9OXPvaSGTvlnVQUY55DlA/kok4krtTSJdfhsYR34rX0m\n 26HLS2eI5Siw71crjfDNcMTE/lz49pIqA6CJplv2vZ13Yb5Do/xyr7oHqrlza5H8shW4\n PfFw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777005042; x=1777609842;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=o688HWl5XrNHYPI7Z2Xn/6ecck2Zhe/qTWuxAA2gZDk=;\n b=hA4kISJ4BfGJQ47BVsNRjEcYvko57aQ7aBzplaXsGuo8/c40YRfKKvOC26i5HzfxGG\n qTRyDpDnOO4AyWVeKfx7dVECiM3ZCtbBramBCnybhRu0thyTii0AjXTOIAE2tSTSxw/t\n NEwqwjckwYFKJyeJqmupPxwXv8bL8bRqotxTAnvfZpmV9A0OgcrJVg78WXPEeQvNgvsm\n TbxCx/MZ6nrV6BrKZHYtFepoflUqYl6uY03lZ5PQ1k17Ul4p3CFir6+7OlbeYHPbXETR\n 3+Y4fCYXUK2uZqnjvBbxn+Q2sJotoml2mnZCCnA2tc/vlY/QXKY9MnK9f2mdQrWnW9XE\n QNoA==","X-Gm-Message-State":"AOJu0YzCZ5AJo1eR9xi/TohHhOHNk2iY/dzBTHAtax201rdMja12o1bT\n U9SwEQlzdV9zk7XYhQO70Gl7xU3OrdzjkR7DUykKfXBj7oKdBefi3XhNHWTTcQMZT2mG1LFolto\n MBz+yC/8=","X-Gm-Gg":"AeBDieuB7lM+nXJzTTH7VzQAWa+B5YsC2J+8tgCxTJ3RV2FHBOVXSMoLVrRrNzcopEU\n H3sDWVTX0w8IaSNm0Zvt7tu/1E8cir0lrClXRnsMvvoiQ/JkzCOCo7tH7T5JuOq9pkBfNKgEvk5\n fme7Kp5xdZaZ2VXuy2QbkSpDnFXs3NcODGUFr0gD1zjkXjRHiOyfCHBImoWzY/ow114nQ3XPR6J\n CoPS4UF38LbYXpcEoKfn5EaHMMWtt0gdmubHc50bLF6nwviMYPnBNbvF8J2DCpWNXE4PVyDaLNI\n PmjpNaXFREWD9Cr0WBmf5GXMqWpJHUDr4q96ln/LTKeJXNryLAJdxDIygxcHVbbjuSdFrI1j9Q6\n xqaH2ZVarZE7sYtUAGqCjDKT0o+FikOCS/HQYci2DzBA+OfJo0whJXGr3DKyNMzInKKdYqSW3Q+\n KfJMGVhWJWehb3Cy0PEEmJard/rnP0oliMc8yVgWCMWihzbAxluGNuGuaf6DUDlw==","X-Received":"by 2002:a05:6870:6111:b0:423:b4e9:b8fa with SMTP id\n 586e51a60fabf-42a99ae67f4mr15681021fac.23.1777005041715;\n Thu, 23 Apr 2026 21:30:41 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org","Subject":"[PATCH v2 04/40] target/arm: Implement FEAT_FAMINMAX for SVE","Date":"Fri, 24 Apr 2026 14:29:38 +1000","Message-ID":"<20260424043014.46305-5-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260424043014.46305-1-richard.henderson@linaro.org>","References":"<20260424043014.46305-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2001:4860:4864:20::2b;\n envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 11 +++++++++++\n target/arm/tcg/helper-sve-defs.h | 14 ++++++++++++++\n target/arm/tcg/sve_helper.c | 8 ++++++++\n target/arm/tcg/translate-sve.c | 2 ++\n target/arm/tcg/sve.decode | 2 ++\n 5 files changed, 37 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex a2ce38faa3..03631018d7 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1549,6 +1549,11 @@ static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id)\n return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_or_sve2(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2(id);\n+}\n+\n static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);\n@@ -1589,6 +1594,12 @@ static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id);\n }\n \n+static inline bool\n+isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id);\n+}\n+\n /*\n * Feature tests for \"does this exist in either 32-bit or 64-bit?\"\n */\ndiff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-defs.h\nindex c3541a8ca8..1eebb64a29 100644\n--- a/target/arm/tcg/helper-sve-defs.h\n+++ b/target/arm/tcg/helper-sve-defs.h\n@@ -3166,3 +3166,17 @@ DEF_HELPER_FLAGS_5(sve2p1_st1ss_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i\n DEF_HELPER_FLAGS_5(sve2p1_st1ss_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n DEF_HELPER_FLAGS_5(sve2p1_st1dd_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n DEF_HELPER_FLAGS_5(sve2p1_st1dd_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n+\n+DEF_HELPER_FLAGS_6(sve2_famax_h, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famax_s, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famax_d, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+\n+DEF_HELPER_FLAGS_6(sve2_famin_h, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famin_s, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famin_d, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\ndiff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c\nindex 062d8881bd..9968600f75 100644\n--- a/target/arm/tcg/sve_helper.c\n+++ b/target/arm/tcg/sve_helper.c\n@@ -4742,6 +4742,14 @@ DO_ZPZZ_FP(sve_fmulx_h, uint16_t, H1_2, helper_advsimd_mulxh)\n DO_ZPZZ_FP(sve_fmulx_s, uint32_t, H1_4, helper_vfp_mulxs)\n DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)\n \n+DO_ZPZZ_FP(sve2_famax_h, uint16_t, H1_2, float16_famax)\n+DO_ZPZZ_FP(sve2_famax_s, uint32_t, H1_4, float32_famax)\n+DO_ZPZZ_FP(sve2_famax_d, uint64_t, H1_8, float64_famax)\n+\n+DO_ZPZZ_FP(sve2_famin_h, uint16_t, H1_2, float16_famin)\n+DO_ZPZZ_FP(sve2_famin_s, uint32_t, H1_4, float32_famin)\n+DO_ZPZZ_FP(sve2_famin_d, uint64_t, H1_8, float64_famin)\n+\n #undef DO_ZPZZ_FP\n \n /* Three-operand expander, with one scalar operand, controlled by\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 5bace3fda1..756c4373b5 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4252,6 +4252,8 @@ DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd)\n DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn)\n DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv)\n DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx)\n+DO_ZPZZ_FP(FAMAX, aa64_sme2_or_sve2_faminmax, sve2_famax)\n+DO_ZPZZ_FP(FAMIN, aa64_sme2_or_sve2_faminmax, sve2_famin)\n \n typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr,\n TCGv_i64, TCGv_ptr, TCGv_i32);\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex ab63cfaa0f..078a085a79 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1130,6 +1130,8 @@ FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm\n FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm\n FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR\n FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm\n+FAMAX 01100101 .. 00 1110 100 ... ..... ..... @rdn_pg_rm\n+FAMIN 01100101 .. 00 1111 100 ... ..... ..... @rdn_pg_rm\n \n # SVE floating-point arithmetic with immediate (predicated)\n FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1\n","prefixes":["v2","04/40"]}