{"id":2227680,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227680/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-40-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-40-richard.henderson@linaro.org>","date":"2026-04-24T04:30:13","name":"[v2,39/40] target/arm: Enable FEAT_LUT for -cpu max","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"749371e39ae6975a541abcc985ac0d5ccf9c8482","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-40-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227680/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227680/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=pG9Ie54G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20V86tPWz1yDD\n\tfor ; Fri, 24 Apr 2026 14:34:24 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Dp-0003ea-Ve; Fri, 24 Apr 2026 00:32:58 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Dn-0003ZN-PW\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:56 -0400","from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Dm-0003rB-8n\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:55 -0400","by mail-oi1-x231.google.com with SMTP id\n 5614622812f47-4670464029eso4103340b6e.2\n for ; Thu, 23 Apr 2026 21:32:53 -0700 (PDT)","from stoup.. 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helo=mail-oi1-x231.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/cpu64.c | 1 +\n docs/system/arm/emulation.rst | 1 +\n 2 files changed, 2 insertions(+)","diff":"diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c\nindex 40ed799fb8..9b974d6f52 100644\n--- a/target/arm/tcg/cpu64.c\n+++ b/target/arm/tcg/cpu64.c\n@@ -1253,6 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj)\n t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */\n t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */\n t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* FEAT_CSSC */\n+ t = FIELD_DP64(t, ID_AA64ISAR2, LUT, 1); /* FEAT_LUT */\n t = FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */\n SET_IDREG(isar, ID_AA64ISAR2, t);\n \ndiff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst\nindex fda73d3d07..b38a188088 100644\n--- a/docs/system/arm/emulation.rst\n+++ b/docs/system/arm/emulation.rst\n@@ -99,6 +99,7 @@ the following architecture extensions:\n - FEAT_LSE (Large System Extensions)\n - FEAT_LSE2 (Large System Extensions v2)\n - FEAT_LSE128 (128-bit Atomics)\n+- FEAT_LUT (Lookup table instructions with 2-bit and 4-bit indices)\n - FEAT_LVA (Large Virtual Address space)\n - FEAT_MEC (Memory Encryption Contexts)\n \n","prefixes":["v2","39/40"]}