{"id":2227679,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227679/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-16-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-16-richard.henderson@linaro.org>","date":"2026-04-24T04:29:49","name":"[v2,15/40] target/arm: Implement ID_AA64FPFR0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"80edb8194ba50409271a7a8c27cbde24e2cb3cc4","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-16-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227679/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227679/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NLHHiaZg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20V32JSYz1yDD\n\tfor ; Fri, 24 Apr 2026 14:34:19 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Cr-0000Az-Ep; Fri, 24 Apr 2026 00:31:57 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CQ-00076M-FF\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:36 -0400","from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CO-0002qI-0H\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:29 -0400","by mail-ot1-x32f.google.com with SMTP id\n 46e09a7af769-7dbca22dbfeso3257300a34.1\n for ; Thu, 23 Apr 2026 21:31:27 -0700 (PDT)","from stoup.. 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helo=mail-ot1-x32f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 9 +++++++++\n target/arm/helper.c | 13 +++++++++++--\n target/arm/cpu-sysregs.h.inc | 1 +\n 3 files changed, 21 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex ddef6fbeb0..df070afdbf 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -401,6 +401,15 @@ FIELD(ID_AA64SMFR0, I16I64, 52, 4)\n FIELD(ID_AA64SMFR0, SMEVER, 56, 4)\n FIELD(ID_AA64SMFR0, FA64, 63, 1)\n \n+FIELD(ID_AA64FPFR0, F8E5M2, 0, 1)\n+FIELD(ID_AA64FPFR0, F8E4M3, 1, 1)\n+FIELD(ID_AA64FPFR0, F8MM4, 26, 1)\n+FIELD(ID_AA64FPFR0, F8MM8, 27, 1)\n+FIELD(ID_AA64FPFR0, F8DP2, 28, 1)\n+FIELD(ID_AA64FPFR0, F8DP4, 29, 1)\n+FIELD(ID_AA64FPFR0, F8FMA, 30, 1)\n+FIELD(ID_AA64FPFR0, F8CVT, 31, 1)\n+\n FIELD(ID_DFR0, COPDBG, 0, 4)\n FIELD(ID_DFR0, COPSDBG, 4, 4)\n FIELD(ID_DFR0, MMAPDBG, 8, 4)\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 6ebd121050..f0f00c6eff 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6510,11 +6510,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n .access = PL1_R, .type = ARM_CP_CONST,\n .accessfn = access_tid3,\n .resetvalue = 0 },\n- { .name = \"ID_AA64PFR7_EL1_RESERVED\", .state = ARM_CP_STATE_AA64,\n+ { .name = \"ID_AA64FPFR0_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,\n .access = PL1_R, .type = ARM_CP_CONST,\n .accessfn = access_tid3,\n- .resetvalue = 0 },\n+ .resetvalue = GET_IDREG(isar, ID_AA64FPFR0) },\n { .name = \"ID_AA64DFR0_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,\n .access = PL1_R, .type = ARM_CP_CONST,\n@@ -6745,6 +6745,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n R_ID_AA64SMFR0_I16I64_MASK |\n R_ID_AA64SMFR0_SMEVER_MASK |\n R_ID_AA64SMFR0_FA64_MASK },\n+ { .name = \"ID_AA64FPFR0_EL1\",\n+ .exported_bits = R_ID_AA64FPFR0_F8E5M2_MASK |\n+ R_ID_AA64FPFR0_F8E4M3_MASK |\n+ R_ID_AA64FPFR0_F8MM4_MASK |\n+ R_ID_AA64FPFR0_F8MM8_MASK |\n+ R_ID_AA64FPFR0_F8DP2_MASK |\n+ R_ID_AA64FPFR0_F8DP4_MASK |\n+ R_ID_AA64FPFR0_F8FMA_MASK |\n+ R_ID_AA64FPFR0_F8CVT_MASK },\n { .name = \"ID_AA64MMFR0_EL1\",\n .exported_bits = R_ID_AA64MMFR0_ECV_MASK,\n .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |\ndiff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc\nindex b99579f773..6e8b335b8f 100644\n--- a/target/arm/cpu-sysregs.h.inc\n+++ b/target/arm/cpu-sysregs.h.inc\n@@ -3,6 +3,7 @@ DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)\n DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)\n DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)\n DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)\n+DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)\n DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)\n DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)\n DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)\n","prefixes":["v2","15/40"]}