{"id":2227676,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227676/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-13-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-13-richard.henderson@linaro.org>","date":"2026-04-24T04:29:46","name":"[v2,12/40] target/arm: Add FPMR_EL to TBFLAGS","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9336d2ddcc8752f7c21c9f6e2d38502d09828545","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-13-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227676/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227676/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BjO+oqXE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20Tf4rK5z1yDD\n\tfor ; Fri, 24 Apr 2026 14:33:58 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Cc-0007T4-MI; Fri, 24 Apr 2026 00:31:42 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CG-00070U-MP\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:22 -0400","from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CC-0002oL-Mx\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:18 -0400","by mail-oa1-x2a.google.com with SMTP id\n 586e51a60fabf-42fbf95cca8so2177218fac.0\n for ; Thu, 23 Apr 2026 21:31:16 -0700 (PDT)","from stoup.. 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Note that only the A64 accessors use\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 3e3094a463..4001f2fc36 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -199,6 +199,8 @@ typedef struct DisasContext {\n uint8_t gm_blocksize;\n /* True if the current insn_start has been updated. */\n bool insn_start_updated;\n+ /* FMPR exception EL or 0 if enabled. */\n+ uint8_t fpmr_el;\n /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */\n uint32_t nv2_redirect_offset;\n } DisasContext;\ndiff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c\nindex 7e6f8d3647..6759b36f28 100644\n--- a/target/arm/tcg/hflags.c\n+++ b/target/arm/tcg/hflags.c\n@@ -237,6 +237,43 @@ static int zt0_exception_el(CPUARMState *env, int el)\n return 0;\n }\n \n+/*\n+ * Return the exception level to which exceptions should be taken for FPMR.\n+ * C.f. the ARM pseudocode function CheckFPMREnabled.\n+ */\n+static int fpmr_exception_el(CPUARMState *env, int el)\n+{\n+ switch (el) {\n+ case 0:\n+ if (el_is_in_host(env, el)) {\n+ if (!(env->cp15.sctlr_el[2] & SCTLR_EnFPM)) {\n+ return 2;\n+ }\n+ break;\n+ }\n+ if (!(env->cp15.sctlr_el[1] & SCTLR_EnFPM)) {\n+ return 1;\n+ }\n+ /* fall through */\n+ case 1:\n+ if (!(arm_hcrx_el2_eff(env) & HCRX_ENFPM)) {\n+ return 2;\n+ }\n+ break;\n+ case 2:\n+ break;\n+ case 3:\n+ return 0;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ if (arm_feature(env, ARM_FEATURE_EL3)\n+ && !(env->cp15.scr_el3 & SCR_ENFPM)) {\n+ return 3;\n+ }\n+ return 0;\n+}\n+\n static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n ARMMMUIdx mmu_idx)\n {\n@@ -500,6 +537,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n }\n }\n \n+ if (cpu_isar_feature(aa64_fpmr, env_archcpu(env))) {\n+ DP_TBFLAG_A64(flags, FPMR_EL, fpmr_exception_el(env, el));\n+ }\n+\n return rebuild_hflags_common(env, fp_el, mmu_idx, flags);\n }\n \ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 9f375b05ca..ef6038e98b 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -10725,6 +10725,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->gcs_en = EX_TBFLAG_A64(tb_flags, GCS_EN);\n dc->gcs_rvcen = EX_TBFLAG_A64(tb_flags, GCS_RVCEN);\n dc->gcsstr_el = EX_TBFLAG_A64(tb_flags, GCSSTR_EL);\n+ dc->fpmr_el = EX_TBFLAG_A64(tb_flags, FPMR_EL);\n dc->vec_len = 0;\n dc->vec_stride = 0;\n dc->cp_regs = arm_cpu->cp_regs;\n","prefixes":["v2","12/40"]}