{"id":2227669,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227669/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-22-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-22-richard.henderson@linaro.org>","date":"2026-04-24T04:29:55","name":"[v2,21/40] target/arm: Split vector-type.h from cpu.h","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"26c1d7f17e59c4323b0f89079f1be8f8b66324c0","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-22-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227669/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227669/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=kU7sPBwo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20Ry2hVjz1yDD\n\tfor ; Fri, 24 Apr 2026 14:32:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Cs-0000HN-9T; Fri, 24 Apr 2026 00:31:58 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Co-0008QI-Ey\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:54 -0400","from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Cm-00036n-Bz\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:54 -0400","by mail-oa1-x2a.google.com with SMTP id\n 586e51a60fabf-42fe552aedeso528659fac.0\n for ; Thu, 23 Apr 2026 21:31:51 -0700 (PDT)","from stoup.. ([172.58.183.19]) by smtp.gmail.com with ESMTPSA id\n 586e51a60fabf-42b9ac54ec5sm18880864fac.13.2026.04.23.21.31.47\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 23 Apr 2026 21:31:50 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777005111; x=1777609911; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=24k+WndXoiq0k6mJkQd6Ra7B0sSV6OLr1icDt0ng834=;\n b=kU7sPBwodQMFdtmJRcBilF9YkaV306Q+DDBoRU/t8WfgdYHOzfoohqjavXO4bMb+Ud\n dj1zAnuU28DsW5yYx9/UH/1JBL28sUzFu7v+rHJNEBzyqFFCRFkogEc2yh9cfbKedexY\n fd5I/ODAopzmbHFEAeA870axtJRidUB8ZKbfdRmHP7bZoXLfedbu84q+iO4c0fSKrHd5\n XBEQNaTNsZR6nN7oH6KBKU1ooHAvdMBiHYBnnSxtRLIS+lAaV5AmOo5Nz9ERUT5LUv3n\n 6gYmJwiV7zBi/AqKxmhkrxDr3/IlxCrLbbXP7EZifNl92PmCBWQny0qHC4ud3D7tUlTJ\n WNXg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777005111; x=1777609911;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=24k+WndXoiq0k6mJkQd6Ra7B0sSV6OLr1icDt0ng834=;\n b=KdJVjeA533gGzXgK3IjFNPVBTUYy3v31Op7r30nwGUvaQoIJnoKGUH1eL7C/wfoOnM\n Zqi0vs+z+BMWI9wimj9XBWaYyokeNFhyjkrpGiEhhJ09SBv5P3wLuDAB1IiSL8kb5QWC\n 4pyYjnnK8UUv7qhWZ23pdTaXc4Gz+qat5DtRWnSv80vFRgY19XUzUp6PuwxSaeG40s+v\n Gv2qrHq1O9B7B8hbrxqliP5Ejc1P7NIvdQacSotCQq+YSpYh9To6/Q/jhymNAf19icsM\n L08aTLP8WjmP2WY8O2u71HNfuyJEv3mRz4TRH6rm/hDyJfSx+ezcsU4WBjWH12QgqkV+\n +zTA==","X-Gm-Message-State":"AOJu0YwtXZyh9yd8Kj4uTH6g/F6KSY4YQMBuKE/kjZLvIFWYOvpdXEoP\n pKbQriWz66I5BPBakBp6zkkk/Hqe3Eox+ocOMz7fF/StjZAeaElGxcvYVPKM+68eVtfG5QH85WL\n 0AtsyANU=","X-Gm-Gg":"AeBDiesIn9/I2h+eYi8nyk0NOKe8+COAIS9gVQn8SwKl5UgwgkwifwwXpJi4PUJ1KOE\n 5AV1nSDGjSltZDFgzIsC1YLzsMudGVVwYtpm71xRzxgw4dgbyEIaXmvG9XbafXcLX/33YsjKXgd\n ZDy3w93vTSrARmEawQLl0caNirhGMo8MOxzG31Q5pW5BY1UBstvvIHYC61aui1bZcWFha96v5uh\n KVUfXMoyG74c2HhvUk0l4pcn5wmwm9Je0zIMdPv/KfsaUpSK4adkAgC7r2VTzmuRNylXluxTjD+\n dU6fSuFVA/1WLjBC6k+SR06lrqDNuM+8r3lGTjTK4whJDeMBU8z6Wq6om0K8+vHFr1qsuc9eT9a\n pMaqVw6O+4odlJdQarav1gEpEGxGf0FA7lTE3okuxGCUyN6YkQqNfIBzdv4uEzt47eW+NYN0kr7\n OYBQtLEnlG79lcJJosLB39hOe678eEvYTqCGtNvrau9HsAwHZ66z0lPBuYX7TucmtHV70K0ts3","X-Received":"by 2002:a05:6870:304a:b0:42d:c200:4204 with SMTP id\n 586e51a60fabf-42dc2007ab8mr8791166fac.18.1777005110929;\n Thu, 23 Apr 2026 21:31:50 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Subject":"[PATCH v2 21/40] target/arm: Split vector-type.h from cpu.h","Date":"Fri, 24 Apr 2026 14:29:55 +1000","Message-ID":"<20260424043014.46305-22-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260424043014.46305-1-richard.henderson@linaro.org>","References":"<20260424043014.46305-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2001:4860:4864:20::2a;\n envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We want to be able to reference ARMVectorType etc from\ncommon code, so move it out of cpu.h.\n\nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Richard Henderson \n---\n target/arm/cpu.h | 38 +---------------------------------\n target/arm/vector-type.h | 44 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 45 insertions(+), 37 deletions(-)\n create mode 100644 target/arm/vector-type.h","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex e78bc1737d..c0c13d37b9 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -35,6 +35,7 @@\n #include \"target/arm/gtimer.h\"\n #include \"target/arm/cpu-sysregs.h\"\n #include \"target/arm/mmuidx.h\"\n+#include \"target/arm/vector-type.h\"\n \n #define EXCP_UDEF 1 /* undefined instruction */\n #define EXCP_SWI 2 /* software interrupt */\n@@ -140,43 +141,6 @@ typedef struct ARMGenericTimer {\n uint64_t ctl; /* Timer Control register */\n } ARMGenericTimer;\n \n-/* Define a maximum sized vector register.\n- * For 32-bit, this is a 128-bit NEON/AdvSIMD register.\n- * For 64-bit, this is a 2048-bit SVE register.\n- *\n- * Note that the mapping between S, D, and Q views of the register bank\n- * differs between AArch64 and AArch32.\n- * In AArch32:\n- * Qn = regs[n].d[1]:regs[n].d[0]\n- * Dn = regs[n / 2].d[n & 1]\n- * Sn = regs[n / 4].d[n % 4 / 2],\n- * bits 31..0 for even n, and bits 63..32 for odd n\n- * (and regs[16] to regs[31] are inaccessible)\n- * In AArch64:\n- * Zn = regs[n].d[*]\n- * Qn = regs[n].d[1]:regs[n].d[0]\n- * Dn = regs[n].d[0]\n- * Sn = regs[n].d[0] bits 31..0\n- * Hn = regs[n].d[0] bits 15..0\n- *\n- * This corresponds to the architecturally defined mapping between\n- * the two execution states, and means we do not need to explicitly\n- * map these registers when changing states.\n- *\n- * Align the data for use with TCG host vector operations.\n- */\n-\n-#define ARM_MAX_VQ 16\n-\n-typedef struct ARMVectorReg {\n- uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);\n-} ARMVectorReg;\n-\n-/* In AArch32 mode, predicate registers do not exist at all. */\n-typedef struct ARMPredicateReg {\n- uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);\n-} ARMPredicateReg;\n-\n /* In AArch32 mode, PAC keys do not exist at all. */\n typedef struct ARMPACKey {\n uint64_t lo, hi;\ndiff --git a/target/arm/vector-type.h b/target/arm/vector-type.h\nnew file mode 100644\nindex 0000000000..d94c0d986e\n--- /dev/null\n+++ b/target/arm/vector-type.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#ifndef TARGET_ARM_VECTOR_TYPE_H\n+#define TARGET_ARM_VECTOR_TYPE_H\n+\n+/*\n+ * Define a maximum sized vector register.\n+ * For 32-bit, this is a 128-bit NEON/AdvSIMD register.\n+ * For 64-bit, this is a 2048-bit SVE register.\n+ *\n+ * Note that the mapping between S, D, and Q views of the register bank\n+ * differs between AArch64 and AArch32.\n+ * In AArch32:\n+ * Qn = regs[n].d[1]:regs[n].d[0]\n+ * Dn = regs[n / 2].d[n & 1]\n+ * Sn = regs[n / 4].d[n % 4 / 2],\n+ * bits 31..0 for even n, and bits 63..32 for odd n\n+ * (and regs[16] to regs[31] are inaccessible)\n+ * In AArch64:\n+ * Zn = regs[n].d[*]\n+ * Qn = regs[n].d[1]:regs[n].d[0]\n+ * Dn = regs[n].d[0]\n+ * Sn = regs[n].d[0] bits 31..0\n+ * Hn = regs[n].d[0] bits 15..0\n+ *\n+ * This corresponds to the architecturally defined mapping between\n+ * the two execution states, and means we do not need to explicitly\n+ * map these registers when changing states.\n+ *\n+ * Align the data for use with TCG host vector operations.\n+ */\n+\n+#define ARM_MAX_VQ 16\n+\n+typedef struct ARMVectorReg {\n+ uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);\n+} ARMVectorReg;\n+\n+/* In AArch32 mode, predicate registers do not exist at all. */\n+typedef struct ARMPredicateReg {\n+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);\n+} ARMPredicateReg;\n+\n+#endif\n","prefixes":["v2","21/40"]}