{"id":2227662,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227662/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-2-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-2-richard.henderson@linaro.org>","date":"2026-04-24T04:29:35","name":"[v2,01/40] target/arm: Implement ID_AA64ISAR3","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f7993da9151e635fc674b63039442f2848834f1b","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-2-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227662/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227662/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Z3d84YEP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20RN2tBXz1yDD\n\tfor ; Fri, 24 Apr 2026 14:32:00 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Bm-0005lC-BT; Fri, 24 Apr 2026 00:30:50 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Be-0005g6-Qh\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:48 -0400","from mail-oa1-x33.google.com ([2001:4860:4864:20::33])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8BU-0002Vx-Vk\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:36 -0400","by mail-oa1-x33.google.com with SMTP id\n 586e51a60fabf-42fc6923f38so1356068fac.1\n for ; Thu, 23 Apr 2026 21:30:31 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x33.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 9 +++++++++\n target/arm/helper.c | 8 ++++++--\n target/arm/cpu-sysregs.h.inc | 1 +\n 3 files changed, 16 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex b683c9551a..b165fe0b1a 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -244,6 +244,15 @@ FIELD(ID_AA64ISAR2, CSSC, 52, 4)\n FIELD(ID_AA64ISAR2, LUT, 56, 4)\n FIELD(ID_AA64ISAR2, ATS1A, 60, 4)\n \n+FIELD(ID_AA64ISAR3, CPA, 0, 4)\n+FIELD(ID_AA64ISAR3, FAMINMAX, 4, 4)\n+FIELD(ID_AA64ISAR3, TLBIW, 8, 4)\n+FIELD(ID_AA64ISAR3, PACM, 12, 4)\n+FIELD(ID_AA64ISAR3, LSFE, 16, 4)\n+FIELD(ID_AA64ISAR3, OCCMO, 20, 4)\n+FIELD(ID_AA64ISAR3, LSUI, 24, 4)\n+FIELD(ID_AA64ISAR3, FPRCVT, 28, 4)\n+\n FIELD(ID_AA64PFR0, EL0, 0, 4)\n FIELD(ID_AA64PFR0, EL1, 4, 4)\n FIELD(ID_AA64PFR0, EL2, 8, 4)\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..08285b69a7 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6552,11 +6552,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n .access = PL1_R, .type = ARM_CP_CONST,\n .accessfn = access_tid3,\n .resetvalue = GET_IDREG(isar, ID_AA64ISAR2)},\n- { .name = \"ID_AA64ISAR3_EL1_RESERVED\", .state = ARM_CP_STATE_AA64,\n+ { .name = \"ID_AA64ISAR3_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,\n .access = PL1_R, .type = ARM_CP_CONST,\n .accessfn = access_tid3,\n- .resetvalue = 0 },\n+ .resetvalue = GET_IDREG(isar, ID_AA64ISAR3) },\n { .name = \"ID_AA64ISAR4_EL1_RESERVED\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,\n .access = PL1_R, .type = ARM_CP_CONST,\n@@ -6785,6 +6785,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n R_ID_AA64ISAR2_BC_MASK |\n R_ID_AA64ISAR2_RPRFM_MASK |\n R_ID_AA64ISAR2_CSSC_MASK },\n+ { .name = \"ID_AA64ISAR3_EL1\",\n+ .exported_bits = R_ID_AA64ISAR3_FAMINMAX_MASK |\n+ R_ID_AA64ISAR3_LSFE_MASK |\n+ R_ID_AA64ISAR3_FPRCVT_MASK },\n { .name = \"ID_AA64ISAR*_EL1_RESERVED\",\n .is_glob = true },\n };\ndiff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc\nindex 3d1ed40f04..b99579f773 100644\n--- a/target/arm/cpu-sysregs.h.inc\n+++ b/target/arm/cpu-sysregs.h.inc\n@@ -10,6 +10,7 @@ DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)\n DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)\n DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)\n DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)\n+DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)\n DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)\n DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)\n DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)\n","prefixes":["v2","01/40"]}