{"id":2227661,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227661/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-18-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-18-richard.henderson@linaro.org>","date":"2026-04-24T04:29:51","name":"[v2,17/40] target/arm: Implement FSCALE for AdvSIMD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a34fa907e5c87046a0b4eb51b362a4ec68396688","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-18-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227661/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227661/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=eL4jT3KE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20RF3Jb3z1yDD\n\tfor ; Fri, 24 Apr 2026 14:31:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Ch-0007in-JA; Fri, 24 Apr 2026 00:31:48 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CZ-0007DK-Ko\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:40 -0400","from mail-oa1-x34.google.com ([2001:4860:4864:20::34])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8CY-0002sx-1f\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:31:39 -0400","by mail-oa1-x34.google.com with SMTP id\n 586e51a60fabf-4094b31a037so4589318fac.1\n for ; Thu, 23 Apr 2026 21:31:36 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x34.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/helper-a64-defs.h | 4 ++++\n target/arm/tcg/vec_internal.h | 4 ++++\n target/arm/tcg/translate-a64.c | 7 +++++++\n target/arm/tcg/vec_helper64.c | 16 ++++++++++++++++\n target/arm/tcg/a64.decode | 3 +++\n 5 files changed, 34 insertions(+)","diff":"diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex eb270cf58b..08ba8a98a1 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -152,6 +152,10 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32\n DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n \n+DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_2(exception_return, void, env, i64)\n #endif\ndiff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex 5c3f51eed3..b647399b18 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -349,6 +349,10 @@ float32 float32_famin(float32, float32, float_status *);\n float64 float64_famax(float64, float64, float_status *);\n float64 float64_famin(float64, float64, float_status *);\n \n+#define float16_fscale float16_scalbn\n+#define float32_fscale float32_scalbn\n+float64 float64_fscale(float64, int64_t, float_status *);\n+\n /*\n * Decode helper functions for predicate as counter.\n */\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex d132e051ca..515c0fb2e0 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -6495,6 +6495,13 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {\n };\n TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[3] = {\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE, aa64_f8cvt, do_fp3_vector, a, 0, f_vector_fscale)\n+\n static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)\n {\n if (fp_access_check(s)) {\ndiff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c\nindex b5ad67b5e0..5479d98daf 100644\n--- a/target/arm/tcg/vec_helper64.c\n+++ b/target/arm/tcg/vec_helper64.c\n@@ -175,3 +175,19 @@ DO_3OP(gvec_famax_s, float32_famax, float32)\n DO_3OP(gvec_famin_s, float32_famin, float32)\n DO_3OP(gvec_famax_d, float64_famax, float64)\n DO_3OP(gvec_famin_d, float64_famin, float64)\n+\n+float64 float64_fscale(float64 n, int64_t m, float_status *s)\n+{\n+ /*\n+ * Given the 'int' parameter of float64_scalbn, we have to saturate\n+ * the 'int64_t' parameter of the operation to some value. Since\n+ * float64 has an 11-bit exponent, saturating to 12 bits is sufficient\n+ * to ensure that DBL_TRUE_MIN can be made to overflow.\n+ */\n+ int sat_m = MIN(MAX(m, -0xfff), 0xfff);\n+ return float64_scalbn(n, sat_m, s);\n+}\n+\n+DO_3OP(gvec_fscale_h, float16_fscale, int16_t)\n+DO_3OP(gvec_fscale_s, float32_fscale, int32_t)\n+DO_3OP(gvec_fscale_d, float64_fscale, int64_t)\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 666a293540..02c7264cb9 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1198,6 +1198,9 @@ FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h\n FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n \n+FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h\n+FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n","prefixes":["v2","17/40"]}