{"id":2227658,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227658/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-4-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260424043014.46305-4-richard.henderson@linaro.org>","date":"2026-04-24T04:29:37","name":"[v2,03/40] target/arm: Implement FEAT_FAMINMAX for SME","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dc4651444e17753b9c5784a75664a7ff567bf5cd","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-4-richard.henderson@linaro.org/mbox/","series":[{"id":501300,"url":"http://patchwork.ozlabs.org/api/1.1/series/501300/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300","date":"2026-04-24T04:29:37","name":"target/arm: Implement FEAT_FP8","version":2,"mbox":"http://patchwork.ozlabs.org/series/501300/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227658/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227658/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CRMk5ZXo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20QC5k5Yz1yDD\n\tfor ; Fri, 24 Apr 2026 14:30:59 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wG8Bl-0005ik-Eb; Fri, 24 Apr 2026 00:30:49 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Bj-0005gG-Tl\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:48 -0400","from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wG8Be-0002XV-Ix\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:30:47 -0400","by mail-oa1-x2d.google.com with SMTP id\n 586e51a60fabf-404254ffe8aso5224906fac.0\n for ; Thu, 23 Apr 2026 21:30:38 -0700 (PDT)","from stoup.. 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helo=mail-oa1-x2d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Since there is no bfloat16 variant of FAMINMAX,\ncheck for missing function pointer in do_z2z_nn_fpst.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sme.c | 23 +++++++++++++++++++++--\n target/arm/tcg/sme.decode | 5 +++++\n 3 files changed, 31 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 7c96b26788..a2ce38faa3 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1574,6 +1574,11 @@ static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_faminmax(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) && isar_feature_aa64_faminmax(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 7d25ac5a51..ca6b130cfe 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -19,6 +19,7 @@\n \n #include \"qemu/osdep.h\"\n #include \"cpu.h\"\n+#include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n #include \"translate.h\"\n@@ -741,9 +742,12 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,\n gen_helper_gvec_3_ptr * const fns[4])\n {\n int esz = a->esz, n, dn, dm, vsz;\n- gen_helper_gvec_3_ptr *fn;\n+ gen_helper_gvec_3_ptr *fn = fns[esz];\n TCGv_ptr fpst;\n \n+ if (fn == NULL) {\n+ return false;\n+ }\n if (esz == MO_8 && !dc_isar_feature(aa64_sme_b16b16, s)) {\n return false;\n }\n@@ -752,7 +756,6 @@ static bool do_z2z_nn_fpst(DisasContext *s, arg_z2z_en *a,\n }\n \n fpst = fpstatus_ptr(esz == MO_16 ? FPST_A64_F16 : FPST_A64);\n- fn = fns[esz];\n n = a->n;\n dn = a->zdn;\n dm = a->zm;\n@@ -811,6 +814,22 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnm[4] = {\n TRANS_FEAT(FMINNM_n1, aa64_sme2, do_z2z_n1_fpst, a, f_vector_fminnm)\n TRANS_FEAT(FMINNM_nn, aa64_sme2, do_z2z_nn_fpst, a, f_vector_fminnm)\n \n+static gen_helper_gvec_3_ptr * const f_vector_famax[4] = {\n+ NULL,\n+ gen_helper_gvec_famax_h,\n+ gen_helper_gvec_famax_s,\n+ gen_helper_gvec_famax_d,\n+};\n+TRANS_FEAT(FAMAX_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famax)\n+\n+static gen_helper_gvec_3_ptr * const f_vector_famin[4] = {\n+ NULL,\n+ gen_helper_gvec_famin_h,\n+ gen_helper_gvec_famin_s,\n+ gen_helper_gvec_famin_d,\n+};\n+TRANS_FEAT(FAMIN_nn, aa64_sme2_faminmax, do_z2z_nn_fpst, a, f_vector_famin)\n+\n /* Add/Sub vector Z[m] to each Z[n*N] with result in ZA[d*N]. */\n static bool do_azz_n1(DisasContext *s, arg_azz_n *a, int esz,\n GVecGen3FnVar *fn)\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 6bb9aa2a90..9dec7318a4 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -286,6 +286,11 @@ URSHL_nn 1100000 1 .. 1 ..... 1011.0 10001 .... 1 @z2z_4x4\n SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_2x2\n SQDMULH_nn 1100000 1 .. 1 ..... 1011.1 00000 .... 0 @z2z_4x4\n \n+FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_2x2\n+FAMAX_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 0 @z2z_4x4\n+FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_2x2\n+FAMIN_nn 1100000 1 .. 1 ..... 1011.0 01010 .... 1 @z2z_4x4\n+\n ### SME2 Multi-vector Multiple and Single Array Vectors\n \n &azz_n n off rv zn zm\n","prefixes":["v2","03/40"]}