{"id":2227635,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227635/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260424025735.1490772-4-hongxing.zhu@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260424025735.1490772-4-hongxing.zhu@nxp.com>","date":"2026-04-24T02:57:35","name":"[v1,3/3] PCI: imx6: Add root port reset to support link recovery","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fcc6b41511b5b8907d27e0edbf98cf9d00fb4036","submitter":{"id":68324,"url":"http://patchwork.ozlabs.org/api/1.1/people/68324/?format=json","name":"Richard Zhu","email":"hongxing.zhu@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260424025735.1490772-4-hongxing.zhu@nxp.com/mbox/","series":[{"id":501288,"url":"http://patchwork.ozlabs.org/api/1.1/series/501288/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=501288","date":"2026-04-24T02:57:33","name":"Add root port reset to support link recovery","version":1,"mbox":"http://patchwork.ozlabs.org/series/501288/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227635/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227635/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 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arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=SU3Dkdp9jiHl5QYOnxTqHHDmI8qJMUyeIFokLxHv6Qk=;\n b=nMMOsGG6qIIjyIaVbtwvqCteTf19YN8dafHzSc05yapb+a7a5HSTqwBwcCGJFU6ygXh982Lh/iWgkCgn/xx/sd5umjanOOLXOM8U1eYHia0uPSURyCYgVgfoqT67Hor+o2vqH5pQy5T39am5knG8ZDx2D0VZU0a9kCCCdZjq0g0YJpR7OhUDsiz3NHSd13FMxNTDhTMBdXprYCBZ1hyOCAm366Rr2mTDFZ3Nu7L9vwL9D03FHcpuVPMFSpYWK4IoKJ5UuLCQDflZRdjkeKAozW1ZhJ6xS0qAsKu0OEKLrOD5QOGygeMaT7T/d7Zu/zz9NUazGzOW4UgpCfZSX/1XIA==","From":"Richard Zhu ","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tbhelgaas@google.com,\n\tfrank.li@nxp.com,\n\tl.stach@pengutronix.de,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com","Cc":"linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\timx@lists.linux.dev,\n\tlinux-kernel@vger.kernel.org,\n\tRichard Zhu ","Subject":"[PATCH v1 3/3] PCI: imx6: Add root port reset to support link\n recovery","Date":"Fri, 24 Apr 2026 10:57:35 +0800","Message-Id":"<20260424025735.1490772-4-hongxing.zhu@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260424025735.1490772-1-hongxing.zhu@nxp.com>","References":"<20260424025735.1490772-1-hongxing.zhu@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA5PR01CA0223.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:a01:1f3::9) To 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2c751684-cb7f-42d1-fcd6-08dea1ad119d","X-MS-Exchange-CrossTenant-AuthSource":"AM6PR04MB5222.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"24 Apr 2026 02:56:23.3745\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n MmqtWHQ1olQuO614V/lKIau2KTdW119he7WZxRyEARielQOh8e5bNoaMMGVTZaeKvWhFZiCQw8MzsBumzB+3sg==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DU2PR04MB8791"},"content":"The PCIe link can go down due to various unexpected circumstances. Add\nroot port reset support to enable link recovery for the i.MX PCIe\ncontroller when the optional \"intr\" interrupt is present.\n\nReset root port to uninitialize, initialize the PCIe controller, and\nrestart the PCIe link at end when a link down event happens.\n\nOn i.MX95 platforms, link events and PME share the same interrupt line.\nThe link event interrupt cannot use a threaded-only IRQ handler because\nthe PME driver uses request_irq() with only the IRQF_SHARED flag set,\nwhich requires a primary handler.\n\nTo handle this shared interrupt scenario, register a primary interrupt\nhandler with IRQF_SHARED for link events and manipulate the link event\nenable bits to ensure the shared interrupt source triggers only one\nhandler at a time.\n\nSigned-off-by: Richard Zhu \n---\n drivers/pci/controller/dwc/pci-imx6.c | 122 ++++++++++++++++++++++++++\n 1 file changed, 122 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex e35044cc52185..0fb75d4b4e636 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -34,6 +34,7 @@\n #include \n \n #include \"../../pci.h\"\n+#include \"../pci-host-common.h\"\n #include \"pcie-designware.h\"\n \n #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n@@ -78,6 +79,10 @@\n #define IMX95_SID_MASK\t\t\t\tGENMASK(5, 0)\n #define IMX95_MAX_LUT\t\t\t\t32\n \n+#define IMX95_LINK_INT_CTRL_STS\t\t\t0x1040\n+#define IMX95_LINK_DOWN_INT_STS\t\t\tBIT(11)\n+#define IMX95_LINK_DOWN_INT_EN\t\t\tBIT(10)\n+\n #define IMX95_PCIE_RST_CTRL\t\t\t0x3010\n #define IMX95_PCIE_COLD_RST\t\t\tBIT(0)\n \n@@ -125,6 +130,8 @@ enum imx_pcie_variants {\n #define IMX_PCIE_MAX_INSTANCES\t2\n \n struct imx_pcie;\n+static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge,\n+\t\t\t\t struct pci_dev *pdev);\n \n struct imx_pcie_drvdata {\n \tenum imx_pcie_variants variant;\n@@ -158,6 +165,7 @@ struct imx_pcie {\n \tbool\t\t\tsupports_clkreq;\n \tbool\t\t\tenable_ext_refclk;\n \tstruct regmap\t\t*iomuxc_gpr;\n+\tu32\t\t\tlnk_intr;\n \tu16\t\t\tmsi_ctrl;\n \tu32\t\t\tcontroller_id;\n \tstruct reset_control\t*pciephy_reset;\n@@ -1306,6 +1314,13 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \n \timx_setup_phy_mpll(imx_pcie);\n \n+\t/*\n+\t * Callback invoked by PCI core when link down is detected and\n+\t * recovery is needed.\n+\t */\n+\tif (pp->bridge)\n+\t\tpp->bridge->reset_root_port = imx_pcie_reset_root_port;\n+\n \treturn 0;\n \n err_phy_off:\n@@ -1573,6 +1588,9 @@ static int imx_pcie_suspend_noirq(struct device *dev)\n \tif (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))\n \t\treturn 0;\n \n+\tif (imx_pcie->lnk_intr)\n+\t\tregmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\t\t IMX95_LINK_DOWN_INT_EN);\n \timx_pcie_msi_save_restore(imx_pcie, true);\n \tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))\n \t\timx_pcie_lut_save(imx_pcie);\n@@ -1623,6 +1641,9 @@ static int imx_pcie_resume_noirq(struct device *dev)\n \tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))\n \t\timx_pcie_lut_restore(imx_pcie);\n \timx_pcie_msi_save_restore(imx_pcie, false);\n+\tif (imx_pcie->lnk_intr)\n+\t\tregmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\t\tIMX95_LINK_DOWN_INT_EN);\n \n \treturn 0;\n }\n@@ -1632,6 +1653,84 @@ static const struct dev_pm_ops imx_pcie_pm_ops = {\n \t\t\t\t imx_pcie_resume_noirq)\n };\n \n+static irqreturn_t imx_pcie_link_irq_handler(int irq, void *priv)\n+{\n+\tstruct imx_pcie *imx_pcie = priv;\n+\tstruct dw_pcie *pci = imx_pcie->pci;\n+\tstruct device *dev = pci->dev;\n+\tu32 val;\n+\n+\tregmap_read(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, &val);\n+\tif (val & IMX95_LINK_DOWN_INT_STS) {\n+\t\tdev_dbg(dev, \"PCIe link down detected, initiating recovery\\n\");\n+\t\tregmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\t\t IMX95_LINK_DOWN_INT_EN);\n+\t\tregmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\t\tIMX95_LINK_DOWN_INT_STS);\n+\n+\t\treturn IRQ_WAKE_THREAD;\n+\t} else {\n+\t\treturn IRQ_NONE;\n+\t}\n+}\n+\n+static irqreturn_t imx_pcie_link_irq_thread(int irq, void *priv)\n+{\n+\tstruct imx_pcie *imx_pcie = priv;\n+\tstruct dw_pcie *pci = imx_pcie->pci;\n+\tstruct dw_pcie_rp *pp = &pci->pp;\n+\tstruct pci_dev *port;\n+\n+\tfor_each_pci_bridge(port, pp->bridge->bus)\n+\t\tif (pci_pcie_type(port) == PCI_EXP_TYPE_ROOT_PORT)\n+\t\t\tpci_host_handle_link_down(port);\n+\n+\tregmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\tIMX95_LINK_DOWN_INT_EN);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge,\n+\t\t\t\t struct pci_dev *pdev)\n+{\n+\tstruct pci_bus *bus = bridge->bus;\n+\tstruct dw_pcie_rp *pp = bus->sysdata;\n+\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n+\tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n+\tint ret;\n+\n+\timx_pcie_msi_save_restore(imx_pcie, true);\n+\tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))\n+\t\timx_pcie_lut_save(imx_pcie);\n+\timx_pcie_stop_link(pci);\n+\timx_pcie_host_exit(pp);\n+\n+\tret = imx_pcie_host_init(pp);\n+\tif (ret) {\n+\t\tdev_err(pci->dev, \"Failed to re-init PCIe\\n\");\n+\t\treturn ret;\n+\t}\n+\tret = dw_pcie_setup_rc(pp);\n+\tif (ret)\n+\t\tgoto err_host_deinit;\n+\n+\timx_pcie_start_link(pci);\n+\tdw_pcie_wait_for_link(pci);\n+\n+\tif (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))\n+\t\timx_pcie_lut_restore(imx_pcie);\n+\timx_pcie_msi_save_restore(imx_pcie, false);\n+\n+\tdev_dbg(pci->dev, \"Root port reset completed\\n\");\n+\treturn 0;\n+\n+err_host_deinit:\n+\timx_pcie_host_exit(pp);\n+\n+\treturn ret;\n+}\n+\n static int imx_pcie_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -1834,9 +1933,32 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \t\t\tval |= PCI_MSI_FLAGS_ENABLE;\n \t\t\tdw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);\n \t\t}\n+\n+\t\t/* Get link event irq if it is present */\n+\t\timx_pcie->lnk_intr = platform_get_irq_byname(pdev, \"intr\");\n+\t\tif (imx_pcie->lnk_intr < 0)\n+\t\t\treturn 0;\n+\n+\t\tret = devm_request_threaded_irq(dev, imx_pcie->lnk_intr,\n+\t\t\t\t\t\timx_pcie_link_irq_handler,\n+\t\t\t\t\t\timx_pcie_link_irq_thread,\n+\t\t\t\t\t\tIRQF_SHARED,\n+\t\t\t\t\t\t\"lnk\", imx_pcie);\n+\t\tif (ret) {\n+\t\t\tdev_err_probe(dev, ret, \"Unable to request LNK IRQ\\n\");\n+\t\t\tgoto err_host_deinit;\n+\t\t}\n+\n+\t\tregmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,\n+\t\t\t\tIMX95_LINK_DOWN_INT_EN);\n \t}\n \n \treturn 0;\n+\n+err_host_deinit:\n+\tdw_pcie_host_deinit(&pci->pp);\n+\n+\treturn ret;\n }\n \n static void imx_pcie_shutdown(struct platform_device *pdev)\n","prefixes":["v1","3/3"]}