{"id":2227428,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227428/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423170229.64655-17-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423170229.64655-17-philmd@linaro.org>","date":"2026-04-23T17:02:28","name":"[RFC,16/16] Reapply \"target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0\"","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4e3c5fffd79900a610226a81a42a2fb3dd040be7","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423170229.64655-17-philmd@linaro.org/mbox/","series":[{"id":501223,"url":"http://patchwork.ozlabs.org/api/1.1/series/501223/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501223","date":"2026-04-23T17:02:12","name":"accel/hvf: Assorted collection of patches queued before v11 release","version":1,"mbox":"http://patchwork.ozlabs.org/series/501223/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227428/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227428/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=PfafYJeP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32d;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This reverts commit 28b0ed32b32c7e5094cf2f1ec9c0645c65fad2aa.\n\nStill not working...\n\n **\n ERROR:../../target/arm/machine.c:1045:cpu_pre_load: assertion failed: (!cpu->cpreg_vmstate_indexes)\n Bail out! ERROR:../../target/arm/machine.c:1045:cpu_pre_load: assertion failed: (!cpu->cpreg_vmstate_indexes)\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/arm/hvf/hvf.c | 42 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 42 insertions(+)","diff":"diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex a905d9bc370..01b2a904c3c 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -201,6 +201,9 @@ void hvf_arm_init_debug(void)\n #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6)\n #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)\n #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)\n+\n+#define SYSREG_CNTV_CTL_EL0 SYSREG(3, 3, 14, 3, 1)\n+#define SYSREG_CNTV_CVAL_EL0 SYSREG(3, 3, 14, 3, 2)\n #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)\n \n #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)\n@@ -731,6 +734,40 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, const char *cpname,\n return false;\n }\n \n+static void hvf_arch_get_vtimer(CPUState *cpu)\n+{\n+ hv_return_t r;\n+ uint64_t val;\n+ bool b;\n+\n+ r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &val);\n+ assert_hvf_ok(r);\n+ b = hvf_sysreg_write_cp(cpu, \"VTimer\", SYSREG_CNTV_CVAL_EL0, val);\n+ assert(b);\n+\n+ r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &val);\n+ assert_hvf_ok(r);\n+ b = hvf_sysreg_write_cp(cpu, \"VTimer\", SYSREG_CNTV_CTL_EL0, val);\n+ assert(b);\n+}\n+\n+static void hvf_arch_put_vtimer(CPUState *cpu)\n+{\n+ hv_return_t r;\n+ uint64_t val;\n+ bool b;\n+\n+ b = hvf_sysreg_read_cp(cpu, \"VTimer\", SYSREG_CNTV_CVAL_EL0, &val);\n+ assert(b);\n+ r = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, val);\n+ assert_hvf_ok(r);\n+\n+ b = hvf_sysreg_read_cp(cpu, \"VTimer\", SYSREG_CNTV_CTL_EL0, &val);\n+ assert(b);\n+ r = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, val);\n+ assert_hvf_ok(r);\n+}\n+\n int hvf_arch_get_registers(CPUState *cpu)\n {\n ARMCPU *arm_cpu = ARM_CPU(cpu);\n@@ -767,6 +804,9 @@ int hvf_arch_get_registers(CPUState *cpu)\n \n ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val);\n assert_hvf_ok(ret);\n+\n+ hvf_arch_get_vtimer(cpu);\n+\n pstate_write(env, val);\n \n for (i = 0, n = arm_cpu->cpreg_array_len; i < n; i++) {\n@@ -929,6 +969,8 @@ int hvf_arch_put_registers(CPUState *cpu)\n ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env));\n assert_hvf_ok(ret);\n \n+ hvf_arch_put_vtimer(cpu);\n+\n aarch64_save_sp(env, arm_current_el(env));\n \n assert(write_cpustate_to_list(arm_cpu, false));\n","prefixes":["RFC","16/16"]}