{"id":2227385,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227385/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com/","project":{"id":35,"url":"http://patchwork.ozlabs.org/api/1.1/projects/35/?format=json","name":"Linux I2C development","link_name":"linux-i2c","list_id":"linux-i2c.vger.kernel.org","list_email":"linux-i2c@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com>","date":"2026-04-23T14:55:50","name":"[v7,3/4] soc: qcom: geni-se: Keep pinctrl active for multi-owner controllers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b309177479fc7ad375bbdad82440dc63046999fd","submitter":{"id":91179,"url":"http://patchwork.ozlabs.org/api/1.1/people/91179/?format=json","name":"Mukesh Kumar Savaliya","email":"mukesh.savaliya@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com/mbox/","series":[{"id":501206,"url":"http://patchwork.ozlabs.org/api/1.1/series/501206/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-i2c/list/?series=501206","date":"2026-04-23T14:55:48","name":"Enable multi-owner I2C support for QCOM GENI controllers","version":7,"mbox":"http://patchwork.ozlabs.org/series/501206/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227385/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227385/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-i2c@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=kY/JaW/8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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arc=none smtp.client-ip=205.220.180.131","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:in-reply-to:message-id\n\t:mime-version:references:subject:to; s=qcppdkim1; bh=MVr+iQ0IOVH\n\toD8QLuy6TdPdop5YCIZQZqq7rbtOLfq4=; b=kY/JaW/81tBDC3bTJ+dVIQt0hSs\n\t1h3N0RZEV68z56FENw+xhRDypU6TI2fCcY0IJlcQ1XSi5i2mkIgmdRQzhoYqUBAz\n\twEF/v6ZUDN+MI1+Dy4DU4tvqX4WccIwe6lcN49Yk5Vme3N+BuLvQI4HEoRnBnBzE\n\t0MMI5vNKMIu4odslVmtFK7yh4ZNqm2nBNOpj94XO4FQZ9boPa7LN5C5TuqnL3XOq\n\t7lwCHx6ltYompWl3AD9bMvU5TH1HyCaEos1xk6I0kKQgP4d4ehQKZh+Pt7E3DCas\n\tfo40XpEPAYZU5MitramtUfru3Omi/WGRK6aaViyQlLYOxRgM1uRY/8Qlb5w==","From":"Mukesh Kumar Savaliya ","To":"viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org,\n krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,\n Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org,\n dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com,\n quic_jseerapu@quicinc.com, agross@kernel.org,\n linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n dmaengine@vger.kernel.org","Cc":"krzysztof.kozlowski@oss.qualcomm.com,\n bartosz.golaszewski@oss.qualcomm.com,\n bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com,\n Mukesh Kumar Savaliya ","Subject":"[PATCH v7 3/4] soc: qcom: geni-se: Keep pinctrl active for\n multi-owner controllers","Date":"Thu, 23 Apr 2026 20:25:50 +0530","Message-ID":"<20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com>","References":"<20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com>","Precedence":"bulk","X-Mailing-List":"linux-i2c@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-QCInternal":["smtphost","smtphost"],"X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfX3wQntq8X80DI\n jdfK1b/mplihxHrqiHMq6M66n4l5ku3HLfiKXQCaiWNqCFmUKtkNuKR6oLOkZf7qUsNiBptMIrp\n UCxeDBsCZyab63xMxAlWJgzPU/EcwHtNUHdrCWyXIbQ6sdWuFfraAK/4aHwuPT2vLEskizDZEnq\n MprEdmwWjRW85/KT86bEyH7N9MI4Pb4f6AjDf0CXTtZw1c1xmU3XldMOs7ltQ8iXXvGBbkq7uHf\n GAY6oPRAt5Ztq4hJOVDyD+CMVAyh6422fIMI4fjoRofKJnlxTcu0WemV0RS0bPCQIK/DWw2UtUZ\n Vd6H64PHc8rxd027gknKFxbDRPXl/TD11M/hyOQqlTUKv5NEOqe2b5pmeyYNvC+QGav8dpF1QyG\n Ys98PQUgJYswh3wjCPoM8PHHrWiL27/Ls8k+1Oxf3abVaChe4aSelZSWPioZMOHUiEq1wV9yAtp\n ABLjXQ+MWblGP3YUmPQ==","X-Authority-Analysis":"v=2.4 cv=OeyoyBTY c=1 sm=1 tr=0 ts=69ea335a cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22\n a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=AU6ItHRBSQEJJjuWNb0A:9","X-Proofpoint-GUID":"yn-QgtGEoKNj2wWp8mn69598A6mtBZow","X-Proofpoint-ORIG-GUID":"yn-QgtGEoKNj2wWp8mn69598A6mtBZow","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0\n clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604230149"},"content":"On platforms where a GENI Serial Engine is shared with another system\nprocessor, selecting the \"sleep\" pinctrl state can disrupt ongoing\ntransfers initiated by the other processor.\n\nTeach geni_se_resources_off() to skip selecting the pinctrl sleep state\nwhen the Serial Engine is marked as shared, while still allowing the\nrest of the resource shutdown sequence to proceed.\n\nThis is required for multi-owner configurations (described via DeviceTree\nwith qcom,qup-multi-owner on the protocol controller node).\n\nReviewed-by: Konrad Dybcio \nSigned-off-by: Mukesh Kumar Savaliya \n---\n drivers/soc/qcom/qcom-geni-se.c | 15 +++++++++++----\n include/linux/soc/qcom/geni-se.h | 2 ++\n 2 files changed, 13 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c\nindex cd1779b6a91a..1a60832ace16 100644\n--- a/drivers/soc/qcom/qcom-geni-se.c\n+++ b/drivers/soc/qcom/qcom-geni-se.c\n@@ -597,10 +597,17 @@ int geni_se_resources_off(struct geni_se *se)\n \n \tif (has_acpi_companion(se->dev))\n \t\treturn 0;\n-\n-\tret = pinctrl_pm_select_sleep_state(se->dev);\n-\tif (ret)\n-\t\treturn ret;\n+\t/*\n+\t * Select the \"sleep\" pinctrl state only when the serial engine is\n+\t * exclusively owned by this system processor. For shared controller\n+\t * configurations, another system processor may still be using the pins,\n+\t * and switching them to \"sleep\" can disrupt ongoing transfers.\n+\t */\n+\tif (!se->multi_owner) {\n+\t\tret = pinctrl_pm_select_sleep_state(se->dev);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n \n \tgeni_se_clks_off(se);\n \treturn 0;\ndiff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h\nindex 0a984e2579fe..46217cac73c3 100644\n--- a/include/linux/soc/qcom/geni-se.h\n+++ b/include/linux/soc/qcom/geni-se.h\n@@ -63,6 +63,7 @@ struct geni_icc_path {\n * @num_clk_levels:\tNumber of valid clock levels in clk_perf_tbl\n * @clk_perf_tbl:\tTable of clock frequency input to serial engine clock\n * @icc_paths:\t\tArray of ICC paths for SE\n+ * @multi_owner:\tTrue if SE is shared between multiple owners.\n */\n struct geni_se {\n \tvoid __iomem *base;\n@@ -72,6 +73,7 @@ struct geni_se {\n \tunsigned int num_clk_levels;\n \tunsigned long *clk_perf_tbl;\n \tstruct geni_icc_path icc_paths[3];\n+\tbool multi_owner;\n };\n \n /* Common SE registers */\n","prefixes":["v7","3/4"]}