{"id":2227370,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227370/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423135035.50126-8-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423135035.50126-8-philmd@linaro.org>","date":"2026-04-23T13:50:33","name":"[7/9] target/s390x: Have MSA helper pass a mmu_idx argument","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e2a5858137796127b45b8cad9f987b562e992bc4","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423135035.50126-8-philmd@linaro.org/mbox/","series":[{"id":501199,"url":"http://patchwork.ozlabs.org/api/1.1/series/501199/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501199","date":"2026-04-23T13:50:26","name":"target/s390x/tcg: Compile various files once","version":1,"mbox":"http://patchwork.ozlabs.org/series/501199/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227370/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227370/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ep9DjWkS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Next commit will use the cpu_ld/st_mmu() API and thus\nwill also use a @mmu_idx. In order to keep it simple to\nreview, propate @mmu_idx in a preliminary step.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/s390x/tcg/crypto_helper.c | 41 +++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 19 deletions(-)","diff":"diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_helper.c\nindex 4447bb66eee..074d745eb3f 100644\n--- a/target/s390x/tcg/crypto_helper.c\n+++ b/target/s390x/tcg/crypto_helper.c\n@@ -18,6 +18,7 @@\n #include \"tcg_s390x.h\"\n #include \"exec/helper-proto.h\"\n #include \"accel/tcg/cpu-ldst.h\"\n+#include \"accel/tcg/cpu-mmu-index.h\"\n \n static uint64_t R(uint64_t x, int c)\n {\n@@ -119,8 +120,8 @@ static void sha512_bda_be64(uint64_t a[8], uint64_t w[16])\n sha512_bda(a, t);\n }\n \n-static void sha512_read_icv(CPUS390XState *env, uint64_t addr,\n- uint64_t a[8], uintptr_t ra)\n+static void sha512_read_icv(CPUS390XState *env, const int mmu_idx,\n+ uint64_t addr, uint64_t a[8], uintptr_t ra)\n {\n int i;\n \n@@ -130,8 +131,8 @@ static void sha512_read_icv(CPUS390XState *env, uint64_t addr,\n }\n }\n \n-static void sha512_write_ocv(CPUS390XState *env, uint64_t addr,\n- uint64_t a[8], uintptr_t ra)\n+static void sha512_write_ocv(CPUS390XState *env, const int mmu_idx,\n+ uint64_t addr, uint64_t a[8], uintptr_t ra)\n {\n int i;\n \n@@ -141,8 +142,8 @@ static void sha512_write_ocv(CPUS390XState *env, uint64_t addr,\n }\n }\n \n-static void sha512_read_block(CPUS390XState *env, uint64_t addr,\n- uint64_t a[16], uintptr_t ra)\n+static void sha512_read_block(CPUS390XState *env, const int mmu_idx,\n+ uint64_t addr, uint64_t a[16], uintptr_t ra)\n {\n int i;\n \n@@ -152,8 +153,8 @@ static void sha512_read_block(CPUS390XState *env, uint64_t addr,\n }\n }\n \n-static void sha512_read_mbl_be64(CPUS390XState *env, uint64_t addr,\n- uint8_t a[16], uintptr_t ra)\n+static void sha512_read_mbl_be64(CPUS390XState *env, const int mmu_idx,\n+ uint64_t addr, uint8_t a[16], uintptr_t ra)\n {\n int i;\n \n@@ -163,8 +164,9 @@ static void sha512_read_mbl_be64(CPUS390XState *env, uint64_t addr,\n }\n }\n \n-static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,\n- uint64_t *message_reg, uint64_t *len_reg, uint32_t type)\n+static int cpacf_sha512(CPUS390XState *env, const int mmu_idx, uintptr_t ra,\n+ uint64_t param_addr, uint64_t *message_reg,\n+ uint64_t *len_reg, uint32_t type)\n {\n enum { MAX_BLOCKS_PER_RUN = 64 }; /* Arbitrary: keep interactivity. */\n uint64_t len = *len_reg, a[8], processed = 0;\n@@ -182,7 +184,7 @@ static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,\n tcg_s390_program_interrupt(env, PGM_SPECIFICATION, ra);\n }\n \n- sha512_read_icv(env, param_addr, a, ra);\n+ sha512_read_icv(env, mmu_idx, param_addr, a, ra);\n \n /* Process full blocks first. */\n for (; len >= 128; len -= 128, processed += 128) {\n@@ -192,7 +194,7 @@ static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,\n break;\n }\n \n- sha512_read_block(env, *message_reg + processed, w, ra);\n+ sha512_read_block(env, mmu_idx, *message_reg + processed, w, ra);\n sha512_bda(a, w);\n }\n \n@@ -215,13 +217,13 @@ static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,\n * or use an additional one.\n */\n if (len < 112) {\n- sha512_read_mbl_be64(env, param_addr + 64, x + 112, ra);\n+ sha512_read_mbl_be64(env, mmu_idx, param_addr + 64, x + 112, ra);\n }\n sha512_bda_be64(a, (uint64_t *)x);\n \n if (len >= 112) {\n memset(x, 0, 112);\n- sha512_read_mbl_be64(env, param_addr + 64, x + 112, ra);\n+ sha512_read_mbl_be64(env, mmu_idx, param_addr + 64, x + 112, ra);\n sha512_bda_be64(a, (uint64_t *)x);\n }\n \n@@ -236,14 +238,14 @@ static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,\n * TODO: if writing fails halfway through (e.g., when crossing page\n * boundaries), we're in trouble. We'd need something like access_prepare().\n */\n- sha512_write_ocv(env, param_addr, a, ra);\n+ sha512_write_ocv(env, mmu_idx, param_addr, a, ra);\n *message_reg = deposit64(*message_reg, 0, message_reg_len,\n *message_reg + processed);\n *len_reg -= processed;\n return !len ? 0 : 3;\n }\n \n-static void fill_buf_random(CPUS390XState *env, uintptr_t ra,\n+static void fill_buf_random(CPUS390XState *env, const int mmu_idx, uintptr_t ra,\n uint64_t *buf_reg, uint64_t *len_reg)\n {\n uint8_t tmp[256];\n@@ -271,6 +273,7 @@ static void fill_buf_random(CPUS390XState *env, uintptr_t ra,\n uint32_t HELPER(msa)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3,\n uint32_t type)\n {\n+ const int mmu_idx = cpu_mmu_index(env_cpu(env), false);\n const uintptr_t ra = GETPC();\n const uint8_t mod = env->regs[0] & 0x80ULL;\n const uint8_t fc = env->regs[0] & 0x7fULL;\n@@ -303,11 +306,11 @@ uint32_t HELPER(msa)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3,\n }\n break;\n case 3: /* CPACF_*_SHA_512 */\n- return cpacf_sha512(env, ra, env->regs[1], &env->regs[r2],\n+ return cpacf_sha512(env, mmu_idx, ra, env->regs[1], &env->regs[r2],\n &env->regs[r2 + 1], type);\n case 114: /* CPACF_PRNO_TRNG */\n- fill_buf_random(env, ra, &env->regs[r1], &env->regs[r1 + 1]);\n- fill_buf_random(env, ra, &env->regs[r2], &env->regs[r2 + 1]);\n+ fill_buf_random(env, mmu_idx, ra, &env->regs[r1], &env->regs[r1 + 1]);\n+ fill_buf_random(env, mmu_idx, ra, &env->regs[r2], &env->regs[r2 + 1]);\n break;\n default:\n /* we don't implement any other subfunction yet */\n","prefixes":["7/9"]}