{"id":2227204,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227204/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-10-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-10-peter.maydell@linaro.org>","date":"2026-04-23T10:01:39","name":"[PULL,09/59] target/arm: Move OMAP CP15 register definitions to cpregs-omap.c","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"0ce3e78a3187614be2a16b5686ebaf26f2452490","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-10-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227204/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227204/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=RZV/iMPR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wtf2Mshz1y2d\n\tfor ; Thu, 23 Apr 2026 20:05:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFqtY-0006MJ-Dv; Thu, 23 Apr 2026 06:02:52 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtQ-0006Jq-Mg\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:45 -0400","from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtO-000201-Gg\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:44 -0400","by mail-wm1-x32a.google.com with SMTP id\n 5b1f17b1804b1-4838c15e3cbso59717235e9.3\n for ; Thu, 23 Apr 2026 03:02:42 -0700 (PDT)","from lanath.. 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Move them out of the monolithic helper.c into a\ndedicated file, following the pattern of cpregs-pmu.c and\ncpregs-gcs.c. This reduces the size of helper.c and compiles\nthe OMAP-specific code out of CONFIG_USER_ONLY builds.\n\nSuggested-by: Paolo Bonzini \nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Alessandro Ratti \nMessage-id: 20260405180826.729652-1-alessandro@0x65c.net\nSigned-off-by: Peter Maydell \n---\n target/arm/cpregs-omap-stub.c | 10 ++++\n target/arm/cpregs-omap.c | 88 +++++++++++++++++++++++++++++++++++\n target/arm/helper.c | 79 +------------------------------\n target/arm/internals.h | 2 +\n target/arm/meson.build | 2 +\n 5 files changed, 103 insertions(+), 78 deletions(-)\n create mode 100644 target/arm/cpregs-omap-stub.c\n create mode 100644 target/arm/cpregs-omap.c","diff":"diff --git a/target/arm/cpregs-omap-stub.c b/target/arm/cpregs-omap-stub.c\nnew file mode 100644\nindex 0000000000..39c511205c\n--- /dev/null\n+++ b/target/arm/cpregs-omap-stub.c\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu-qom.h\"\n+#include \"internals.h\"\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/cpregs-omap.c b/target/arm/cpregs-omap.c\nnew file mode 100644\nindex 0000000000..ac855baada\n--- /dev/null\n+++ b/target/arm/cpregs-omap.c\n@@ -0,0 +1,88 @@\n+/*\n+ * QEMU ARM OMAP CP15 register definitions\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu.h\"\n+#include \"target/arm/cpregs.h\"\n+#include \"target/arm/internals.h\"\n+\n+static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_ticonfig = value & 0xe7;\n+ /* The OS_TYPE bit in this register changes the reported CPUID! */\n+ env->cp15.c0_cpuid = (value & (1 << 5)) ?\n+ ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n+}\n+\n+static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_threadid = value & 0xffff;\n+}\n+\n+static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /* Wait-for-interrupt (deprecated) */\n+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n+}\n+\n+static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * On OMAP there are registers indicating the max/min index of dcache lines\n+ * containing a dirty line; cache flush operations have to reset these.\n+ */\n+ env->cp15.c15_i_max = 0x000;\n+ env->cp15.c15_i_min = 0xff0;\n+}\n+\n+static const ARMCPRegInfo omap_cp_reginfo[] = {\n+ { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n+ .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n+ .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n+ .resetvalue = 0, },\n+ { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .type = ARM_CP_NOP },\n+ { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n+ .writefn = omap_ticonfig_write },\n+ { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n+ { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .resetvalue = 0xff0,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n+ { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n+ .writefn = omap_threadid_write },\n+ { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n+ .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n+ .type = ARM_CP_NO_RAW,\n+ .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n+ /*\n+ * TODO: Peripheral port remap register:\n+ * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n+ * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n+ * when MMU is off.\n+ */\n+ { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n+ .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n+ .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n+ .writefn = omap_cachemaint_write },\n+ { .name = \"C9\", .cp = 15, .crn = 9,\n+ .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n+ .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n+};\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ define_arm_cp_regs(cpu, omap_cp_reginfo);\n+}\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..3ac88078aa 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -2900,83 +2900,6 @@ static const ARMCPRegInfo ttbcr2_reginfo = {\n },\n };\n \n-static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_ticonfig = value & 0xe7;\n- /* The OS_TYPE bit in this register changes the reported CPUID! */\n- env->cp15.c0_cpuid = (value & (1 << 5)) ?\n- ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n-}\n-\n-static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_threadid = value & 0xffff;\n-}\n-\n-static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n-#ifdef CONFIG_USER_ONLY\n- g_assert_not_reached();\n-#else\n- /* Wait-for-interrupt (deprecated) */\n- cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n-#endif\n-}\n-\n-static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- /*\n- * On OMAP there are registers indicating the max/min index of dcache lines\n- * containing a dirty line; cache flush operations have to reset these.\n- */\n- env->cp15.c15_i_max = 0x000;\n- env->cp15.c15_i_min = 0xff0;\n-}\n-\n-static const ARMCPRegInfo omap_cp_reginfo[] = {\n- { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n- .resetvalue = 0, },\n- { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .type = ARM_CP_NOP },\n- { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n- .writefn = omap_ticonfig_write },\n- { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n- { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .resetvalue = 0xff0,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n- { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n- .writefn = omap_threadid_write },\n- { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n- .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n- .type = ARM_CP_NO_RAW,\n- .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n- /*\n- * TODO: Peripheral port remap register:\n- * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n- * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n- * when MMU is off.\n- */\n- { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n- .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n- .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n- .writefn = omap_cachemaint_write },\n- { .name = \"C9\", .cp = 15, .crn = 9,\n- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n- .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n-};\n-\n static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {\n /*\n * RAZ/WI the whole crn=15 space, when we don't have a more specific\n@@ -7043,7 +6966,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);\n }\n if (arm_feature(env, ARM_FEATURE_OMAPCP)) {\n- define_arm_cp_regs(cpu, omap_cp_reginfo);\n+ define_omap_cp_regs(cpu);\n }\n if (arm_feature(env, ARM_FEATURE_STRONGARM)) {\n define_arm_cp_regs(cpu, strongarm_cp_reginfo);\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 85980f0e69..6b16f1a560 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1799,6 +1799,8 @@ void define_at_insn_regs(ARMCPU *cpu);\n void define_pm_cpregs(ARMCPU *cpu);\n /* Add the cpreg definitions for GCS cpregs */\n void define_gcs_cpregs(ARMCPU *cpu);\n+/* Add the cpreg definitions for OMAP CP15 regs */\n+void define_omap_cp_regs(ARMCPU *cpu);\n \n /* Effective value of MDCR_EL2 */\n static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 6e0e504a40..192ac7c31e 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -33,6 +33,7 @@ arm_user_ss.add(files(\n 'helper.c',\n 'vfp_fpscr.c',\n 'el2-stubs.c',\n+ 'cpregs-omap-stub.c',\n ))\n arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',\n \t\t if_true: files('common-semi-target.c'))\n@@ -48,6 +49,7 @@ arm_common_system_ss.add(files(\n 'arm-powerctl.c',\n 'cortex-regs.c',\n 'cpregs-gcs.c',\n+ 'cpregs-omap.c',\n 'cpregs-pmu.c',\n 'cpu-irq.c',\n 'debug_helper.c',\n","prefixes":["PULL","09/59"]}