{"id":2227196,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227196/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-22-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-22-peter.maydell@linaro.org>","date":"2026-04-23T10:01:51","name":"[PULL,21/59] target/arm/tcg/translate.c: replace target_ulong with uint32_t","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"d59c92651f6816acc88527dd6e9de5fccd799d57","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-22-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227196/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227196/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=h4XJK+dw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wt35klSz1yD5\n\tfor ; Thu, 23 Apr 2026 20:04:59 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFqtf-0006Qu-18; Thu, 23 Apr 2026 06:02:59 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtc-0006Pj-T3\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:56 -0400","from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtb-00024u-Cy\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:56 -0400","by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-43d73422431so5467998f8f.2\n for ; Thu, 23 Apr 2026 03:02:54 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Pierrick Bouvier \n\nReviewed-by: Richard Henderson \nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Pierrick Bouvier \nMessage-id: 20260407222208.271838-13-pierrick.bouvier@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/tcg/translate.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 4546bbeeef..204f965799 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -6450,7 +6450,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n * fields here.\n */\n uint32_t condexec_bits;\n- target_ulong pc_arg = dc->base.pc_next;\n+ uint32_t pc_arg = dc->base.pc_next;\n \n if (tb_cflags(dcbase->tb) & CF_PCREL) {\n pc_arg &= ~TARGET_PAGE_MASK;\n@@ -6612,7 +6612,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n bool is_16bit;\n /* TCG op to rewind to if this turns out to be an invalid ECI state */\n TCGOp *insn_eci_rewind = NULL;\n- target_ulong insn_eci_pc_save = -1;\n+ uint32_t insn_eci_pc_save = -1;\n \n /* Misaligned thumb PC is architecturally impossible. */\n assert((dc->base.pc_next & 1) == 0);\n","prefixes":["PULL","21/59"]}