{"id":2227194,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227194/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-25-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-25-peter.maydell@linaro.org>","date":"2026-04-23T10:01:54","name":"[PULL,24/59] target/arm/tcg/translate.c: replace TCGv with TCGv_va","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"43d6db1b859699cffe62ed44fd7908c498652aa1","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-25-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227194/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227194/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZW2rQM7k;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wsy1fyCz1yGs\n\tfor ; Thu, 23 Apr 2026 20:04:54 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFquS-0006tO-Qa; Thu, 23 Apr 2026 06:03:48 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqth-0006Sj-7m\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:03:02 -0400","from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtf-00026H-CL\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:03:00 -0400","by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-43cfbd17589so5143536f8f.0\n for ; Thu, 23 Apr 2026 03:02:58 -0700 (PDT)","from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e4eec9sm49323930f8f.34.2026.04.23.03.02.56\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 23 Apr 2026 03:02:56 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776938578; x=1777543378; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=tBdjRjEK2VHM/TQcuD55BbI0c9Tl7lLp8FbZsgY7OSc=;\n b=ZW2rQM7kORhk4Ic3Bzxh6cSMF08Bey8ZaRZzPDaAeVMTUGSN8tyyuqLQfgrGp4hbrl\n 3CWAqEGi729+cSLzJL9m99ASCr9irhx0Q0spjzIrlOt/ydGm97aC+S8PnKWbIlaJfQlQ\n UPcX9/FmcRft3zpGhPZznUbJQEAap2clqUkctb9WkuYtFI3m6lA5r8wTmq7YIN1xxL1C\n 1uRszyb/jdBeqI5nfDZBUvIaDP1tM2AnwKQhWOvbGlO7xd/bIkJYC7bdA0+i8e4jq0ZD\n DFoH+v+XaCmd+HzVtctKZyHhN1bnSkqBmCivAvFxDkraEPsr4tvsCOIkQc/FH1DASpI4\n H0cw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776938578; x=1777543378;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=tBdjRjEK2VHM/TQcuD55BbI0c9Tl7lLp8FbZsgY7OSc=;\n b=dftYF14C/kzQAllXOIoHi47imY0NBjpG6QIjPWWqORyNNXXNEK+tMtQor2KGAOAZWt\n CnXYB0VViEsfQNCw/OhNXzB8vQhM60KKD0GAv588CRSv1tqonWLWfgN8jfIQpld5s3Bm\n eRXYILPHjdRnkhQr4BbdLAxWYaEepHE3NWnkcMNjdTM88TWSk2JReN0oFBCgvbfi3USn\n EqltiSrROmO+YrJl2VxrV+ybLk6dL9Blx0+4TLNsxPNTVQfDbGnIB3ziyG9aHvDvPzd7\n 6IdfUwjOgAM8TgPc3JD1ryJJhrL0aC5sVUnJTT3Y6Gw7s31KLsAUaUt5Jy6Vtvmt+OIR\n KXKw==","X-Gm-Message-State":"AOJu0YyYG7xt0Ur8JBRanYLhqYDm/QV4KZCmtvY3rQcdBRPthsztl62g\n 7QpyFiL2XiQ9FkHla4H2hUsHxACeDCU3rE/kCBXyJTczSVqZ/FD/AioF8REHq/5wIYXWc6Lf/qh\n ChrHp","X-Gm-Gg":"AeBDiesb8veFe7z66SEistrFjoCMm3fEd9r9+hx78FCETlhQErpsLwIiwNptcH0jY6V\n NXjTKQKQw2fbyzRZwFmMIzPT3gf/0XiAjQcQFWehuUNxBfEtcK/W5ZCmCsdslt4si9N4AKGMGpI\n tVIyUOMcmS3QH7jFq+DWDc/GE99Ls5TZPQClzxC8H1jyv/2rPPI/kbPbXEfUq9s5+d9m+PPmSU2\n i8AclK+qMfSCf8QtbdgJRnzjWKEsoBqq8qWrrCtony/Seg9Qr2iqi+4M5JwBUc69e8FAG0so9dK\n OfR7hj373QLObcKH3wA/P4jLMSpt6YVq7VIXMWTlBLvavGTlw9TUO4jbQ4ZLVCwM2WsY7Ymd/+Z\n +JUOTZAlxGT2z5o4KsWnpVlndcvwt1CwkdTy0Z+vLankefSsPLtarLTc26sr1YJcVkjZjG2G+Ji\n y1+oNPy7LGS4QKhtBH7oK+cFTZwmARsswv2IbrcKMtgCvNrMMN+OtByb8zyE5WY2r2fxmV7jccE\n ZlsfqLoJgGjtM8mtpJ8eJ6Ayr8DF8O+eM6Go34VTA==","X-Received":"by 2002:a05:6000:2081:b0:43b:5022:7fa with SMTP id\n ffacd0b85a97d-43fe3db2e6emr40332811f8f.13.1776938577663;\n Thu, 23 Apr 2026 03:02:57 -0700 (PDT)","From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Subject":"[PULL 24/59] target/arm/tcg/translate.c: replace TCGv with TCGv_va","Date":"Thu, 23 Apr 2026 11:01:54 +0100","Message-ID":"<20260423100229.2941820-25-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260423100229.2941820-1-peter.maydell@linaro.org>","References":"<20260423100229.2941820-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42a;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Pierrick Bouvier \n\nWe know this file is for 32-bit runtime target, so we can set\nTCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already\npassed to translator_loop.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \nReviewed-by: Philippe Mathieu-Daudé \nMessage-id: 20260407222208.271838-16-pierrick.bouvier@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/tcg/translate.c | 29 +++++++++++++++--------------\n 1 file changed, 15 insertions(+), 14 deletions(-)","diff":"diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex fa4c7907dc..0b3b4ab86b 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -22,7 +22,8 @@\n \n #include \"translate.h\"\n #include \"translate-a32.h\"\n-#include \"tcg/tcg-op.h\"\n+#define TCG_ADDRESS_BITS 32\n+#include \"tcg/tcg-op-mem.h\"\n #include \"qemu/log.h\"\n #include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n@@ -910,14 +911,14 @@ MemOp pow2_align(unsigned i)\n * that the address argument is TCGv_i32 rather than TCGv.\n */\n \n-static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n+static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n {\n- TCGv addr = tcg_temp_new();\n- tcg_gen_extu_i32_tl(addr, a32);\n+ TCGv_va addr = tcgv_va_temp_new();\n+ tcg_gen_mov_i32(addr, a32);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {\n- tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));\n+ tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE)));\n }\n return addr;\n }\n@@ -929,21 +930,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)\n void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_ld_i32(val, addr, index, opc);\n }\n \n void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n tcg_gen_qemu_st_i32(val, addr, index, opc);\n }\n \n void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n tcg_gen_qemu_ld_i64(val, addr, index, opc);\n \n@@ -956,7 +957,7 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,\n void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,\n TCGv_i32 a32, int index, MemOp opc)\n {\n- TCGv addr = gen_aa32_addr(s, a32, opc);\n+ TCGv_va addr = gen_aa32_addr(s, a32, opc);\n \n /* Not needed for user-mode BE32, where we use MO_BE instead. */\n if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {\n@@ -2036,7 +2037,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,\n * architecturally 64-bit access, but instead do a 64-bit access\n * using MO_BE if appropriate and then split the two halves.\n */\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n \n tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc);\n tcg_gen_mov_i64(cpu_exclusive_val, t64);\n@@ -2065,7 +2066,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n {\n TCGv_i32 t0, t1, t2;\n TCGv_i64 extaddr;\n- TCGv taddr;\n+ TCGv_va taddr;\n TCGLabel *done_label;\n TCGLabel *fail_label;\n MemOp opc = size | MO_ALIGN | s->be_data;\n@@ -3792,7 +3793,7 @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i64 t64 = tcg_temp_new_i64();\n TCGv_i32 tmp = tcg_temp_new_i32();\n TCGv_i32 tmp2 = tcg_temp_new_i32();\n@@ -3847,7 +3848,7 @@ static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)\n */\n int mem_idx = get_mem_index(s);\n MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;\n- TCGv taddr = gen_aa32_addr(s, addr, opc);\n+ TCGv_va taddr = gen_aa32_addr(s, addr, opc);\n TCGv_i32 t1 = load_reg(s, rt);\n TCGv_i32 t2 = load_reg(s, rt2);\n TCGv_i64 t64 = tcg_temp_new_i64();\n@@ -4068,7 +4069,7 @@ DO_LDST(STRH, store, MO_UW)\n static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc)\n {\n TCGv_i32 addr, tmp;\n- TCGv taddr;\n+ TCGv_va taddr;\n \n opc |= s->be_data;\n addr = load_reg(s, a->rn);\n","prefixes":["PULL","24/59"]}