{"id":2227191,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227191/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-3-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-3-peter.maydell@linaro.org>","date":"2026-04-23T10:01:32","name":"[PULL,02/59] hw/core/machine: topology functions capabilities added","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"f64c216255ff898dc50cd74380efc8e6e068f26e","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-3-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227191/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227191/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Q3YQHn/H;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wsl0fQ9z1yGs\n\tfor ; Thu, 23 Apr 2026 20:04:42 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFqtR-0006Jl-4R; Thu, 23 Apr 2026 06:02:45 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtK-0006IG-Kg\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:39 -0400","from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtH-0001t3-Op\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:38 -0400","by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-43d03db7f87so4400704f8f.3\n for ; Thu, 23 Apr 2026 03:02:35 -0700 (PDT)","from lanath.. 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helo=mail-wr1-x42a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alireza Sanaee \n\nAdd two functions one of which finds the lowest cache level defined in\nthe cache description input, and the other checks if a given cache\ntopology is defined at a particular cache level\n\nReviewed-by: Jonathan Cameron \nSigned-off-by: Alireza Sanaee \nReviewed-by: Gustavo Romero \nMessage-id: 20260311160609.358-3-alireza.sanaee@huawei.com\nSigned-off-by: Peter Maydell \n---\n hw/core/machine-smp.c | 52 ++++++++++++++++++++++++++++++++++++++++\n include/hw/core/boards.h | 5 ++++\n 2 files changed, 57 insertions(+)","diff":"diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c\nindex 189c70015f..bef04aa2d7 100644\n--- a/hw/core/machine-smp.c\n+++ b/hw/core/machine-smp.c\n@@ -406,3 +406,55 @@ bool machine_check_smp_cache(const MachineState *ms, Error **errp)\n \n return true;\n }\n+\n+/*\n+ * This function assumes L3 and L2 have unified cache and L1 is split L1d and\n+ * L1i.\n+ */\n+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,\n+ int *lowest_cache_level,\n+ CpuTopologyLevel topo_level)\n+{\n+ enum CacheLevelAndType cache_level;\n+ enum CpuTopologyLevel t;\n+\n+ for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;\n+ cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {\n+ t = machine_get_cache_topo_level(ms, cache_level);\n+ if (t == topo_level) {\n+ /* Assume L1 is split into L1d and L1i caches. */\n+ if (cache_level == CACHE_LEVEL_AND_TYPE_L1D ||\n+ cache_level == CACHE_LEVEL_AND_TYPE_L1I) {\n+ *lowest_cache_level = 1; /* L1 */\n+ } else {\n+ /* Assume the other caches are unified. */\n+ *lowest_cache_level = cache_level;\n+ }\n+\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\n+\n+/*\n+ * Check if there are caches defined at a particular level. It supports only\n+ * L1, L2 and L3 caches, but this can be extended to more levels as needed.\n+ *\n+ * Return True on success, False otherwise.\n+ */\n+bool machine_defines_cache_at_topo_level(const MachineState *ms,\n+ CpuTopologyLevel topology)\n+{\n+ enum CacheLevelAndType cache_level;\n+\n+ for (cache_level = CACHE_LEVEL_AND_TYPE_L1D;\n+ cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) {\n+ if (machine_get_cache_topo_level(ms, cache_level) == topology) {\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\ndiff --git a/include/hw/core/boards.h b/include/hw/core/boards.h\nindex b8dad0a107..f38b3f5f78 100644\n--- a/include/hw/core/boards.h\n+++ b/include/hw/core/boards.h\n@@ -60,6 +60,11 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,\n CpuTopologyLevel level);\n bool machine_check_smp_cache(const MachineState *ms, Error **errp);\n void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);\n+bool machine_defines_cache_at_topo_level(const MachineState *ms,\n+ CpuTopologyLevel topology);\n+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,\n+ int *lowest_cache_level,\n+ CpuTopologyLevel topo_level);\n \n /**\n * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices\n","prefixes":["PULL","02/59"]}