{"id":2227178,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227178/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-14-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-14-peter.maydell@linaro.org>","date":"2026-04-23T10:01:43","name":"[PULL,13/59] target/arm/tcg/translate.h: remove TARGET_AARCH64","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"7bebf03006ca3afcc8589ca70c5ddaad13b6012c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-14-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227178/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227178/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=kM9GKcX2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1WrY3zLWz1yD5\n\tfor ; Thu, 23 Apr 2026 20:03:41 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFqtX-0006Lt-VR; Thu, 23 Apr 2026 06:02:51 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtV-0006LD-1h\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:49 -0400","from mail-wr1-x429.google.com ([2a00:1450:4864:20::429])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtT-00021m-BD\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:48 -0400","by mail-wr1-x429.google.com with SMTP id\n ffacd0b85a97d-43cfde3c3f3so6632854f8f.3\n for ; Thu, 23 Apr 2026 03:02:46 -0700 (PDT)","from lanath.. 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::429;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Pierrick Bouvier \n\nWe need to stub a64_translate_init and gen_a64_update_pc.\nAt this point, we don't need to do anything for aarch64_translator_ops\nsince it's just an external symbol.\n\nWe can now include target/arm/tcg/translate.h from common code, since\nall target specific bits have been removed, or can be specialized with\nspecific defines.\n\nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \nMessage-id: 20260407222208.271838-5-pierrick.bouvier@linaro.org\nSigned-off-by: Peter Maydell \n---\n target/arm/tcg/meson.build | 1 +\n target/arm/tcg/stubs32.c | 17 +++++++++++++++++\n target/arm/tcg/translate.h | 10 ----------\n 3 files changed, 18 insertions(+), 10 deletions(-)\n create mode 100644 target/arm/tcg/stubs32.c","diff":"diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 5f59156055..3e96c77df7 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -21,6 +21,7 @@ gen_a32 = [\n \n arm_ss.add(gen_a32)\n arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)\n+arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c'))\n \n arm_ss.add(files(\n 'cpu32.c',\ndiff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\nnew file mode 100644\nindex 0000000000..c5a0bc61f4\n--- /dev/null\n+++ b/target/arm/tcg/stubs32.c\n@@ -0,0 +1,17 @@\n+/*\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/tcg/translate.h\"\n+\n+\n+void gen_a64_update_pc(DisasContext *s, int64_t diff)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void a64_translate_init(void)\n+{\n+ /* Don't initialize for 32 bits. Call site will be fixed later. */\n+}\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex e28eac54af..77fdc5f3a1 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -357,19 +357,9 @@ static inline int curr_insn_len(DisasContext *s)\n /* CPU state was modified dynamically; no need to exit, but do not chain. */\n #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10\n \n-#ifdef TARGET_AARCH64\n void a64_translate_init(void);\n void gen_a64_update_pc(DisasContext *s, int64_t diff);\n extern const TranslatorOps aarch64_translator_ops;\n-#else\n-static inline void a64_translate_init(void)\n-{\n-}\n-\n-static inline void gen_a64_update_pc(DisasContext *s, int64_t diff)\n-{\n-}\n-#endif\n \n void arm_test_cc(DisasCompare *cmp, int cc);\n void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);\n","prefixes":["PULL","13/59"]}