{"id":2227175,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2227175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-6-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260423100229.2941820-6-peter.maydell@linaro.org>","date":"2026-04-23T10:01:35","name":"[PULL,05/59] acpi: Add parameters to pass cache descriptions to ACPI build_pptt()","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":false,"hash":"c26580865d8c68b8035d68a19998dc01b40008c5","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-6-peter.maydell@linaro.org/mbox/","series":[{"id":501172,"url":"http://patchwork.ozlabs.org/api/1.1/series/501172/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172","date":"2026-04-23T10:01:35","name":"[PULL,01/59] target/arm/tcg: increase cache level for cpu=max","version":1,"mbox":"http://patchwork.ozlabs.org/series/501172/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2227175/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2227175/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YLSoPJo7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1WrL1M3Zz1yD5\n\tfor ; Thu, 23 Apr 2026 20:03:28 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFqtU-0006LB-Mv; Thu, 23 Apr 2026 06:02:48 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtM-0006Iv-8u\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:41 -0400","from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFqtK-0001xW-KN\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:40 -0400","by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-43cfde3c3f3so6632686f8f.3\n for ; Thu, 23 Apr 2026 03:02:38 -0700 (PDT)","from lanath.. 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helo=mail-wr1-x42f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alireza Sanaee \n\nAdd optional parameters to pass cache descriptions to build_pptt().\nUpdate ARM and Loongarch callers to pass none for now.\n\nReviewed-by: Gustavo Romero \nReviewed-by: Jonathan Cameron \nSigned-off-by: Alireza Sanaee \nMessage-id: 20260311160609.358-6-alireza.sanaee@huawei.com\nSigned-off-by: Peter Maydell \n---\n hw/acpi/aml-build.c | 3 ++-\n hw/arm/virt-acpi-build.c | 2 +-\n hw/loongarch/virt-acpi-build.c | 4 ++--\n include/hw/acpi/aml-build.h | 4 +++-\n 4 files changed, 8 insertions(+), 5 deletions(-)","diff":"diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c\nindex 4b37405088..b0ea8a5d5d 100644\n--- a/hw/acpi/aml-build.c\n+++ b/hw/acpi/aml-build.c\n@@ -2155,7 +2155,8 @@ void build_spcr(GArray *table_data, BIOSLinker *linker,\n * 5.2.29 Processor Properties Topology Table (PPTT)\n */\n void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n- const char *oem_id, const char *oem_table_id)\n+ const char *oem_id, const char *oem_table_id,\n+ int num_caches, CPUCoreCaches *caches)\n {\n MachineClass *mc = MACHINE_GET_CLASS(ms);\n CPUArchIdList *cpus = ms->possible_cpus;\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 591cfc993c..cd0700416e 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -1277,7 +1277,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)\n if (!vmc->no_cpu_topology) {\n acpi_add_table(table_offsets, tables_blob);\n build_pptt(tables_blob, tables->linker, ms,\n- vms->oem_id, vms->oem_table_id);\n+ vms->oem_id, vms->oem_table_id, 0, NULL);\n }\n \n acpi_add_table(table_offsets, tables_blob);\ndiff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c\nindex 3e34bedcd6..a0b445f297 100644\n--- a/hw/loongarch/virt-acpi-build.c\n+++ b/hw/loongarch/virt-acpi-build.c\n@@ -538,8 +538,8 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)\n build_madt(tables_blob, tables->linker, lvms);\n \n acpi_add_table(table_offsets, tables_blob);\n- build_pptt(tables_blob, tables->linker, machine,\n- lvms->oem_id, lvms->oem_table_id);\n+ build_pptt(tables_blob, tables->linker, machine, lvms->oem_id,\n+ lvms->oem_table_id, 0, NULL);\n \n acpi_add_table(table_offsets, tables_blob);\n build_srat(tables_blob, tables->linker, machine);\ndiff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h\nindex f38e129719..e70e0643b1 100644\n--- a/include/hw/acpi/aml-build.h\n+++ b/include/hw/acpi/aml-build.h\n@@ -3,6 +3,7 @@\n \n #include \"hw/acpi/acpi-defs.h\"\n #include \"hw/acpi/bios-linker-loader.h\"\n+#include \"hw/core/cpu.h\"\n \n #define ACPI_BUILD_APPNAME6 \"BOCHS \"\n #define ACPI_BUILD_APPNAME8 \"BXPC \"\n@@ -499,7 +500,8 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n const char *oem_id, const char *oem_table_id);\n \n void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n- const char *oem_id, const char *oem_table_id);\n+ const char *oem_id, const char *oem_table_id,\n+ int num_caches, CPUCoreCaches *caches);\n \n void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,\n const char *oem_id, const char *oem_table_id);\n","prefixes":["PULL","05/59"]}