{"id":2226484,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226484/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-30-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-30-alex.bennee@linaro.org>","date":"2026-04-22T12:52:46","name":"[v3,29/32] target/arm: implement global monitor events","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"de78f4173d1f4fd933fe2c213fa0cbbe9d35ca43","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-30-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226484/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226484/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HtVBWNOO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g101B6DDDz1yD5\n\tfor ; Wed, 22 Apr 2026 23:09:18 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFXK2-0001bn-Ox; Wed, 22 Apr 2026 09:08:54 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFXJy-0001ax-5S\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 09:08:50 -0400","from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFXJv-0003MY-Ty\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 09:08:49 -0400","by mail-lj1-x22d.google.com with SMTP id\n 38308e7fff4ca-38a01c80c34so51208881fa.0\n for ; Wed, 22 Apr 2026 06:08:47 -0700 (PDT)","from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e46898sm47674480f8f.27.2026.04.22.06.02.29\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 22 Apr 2026 06:02:30 -0700 (PDT)","from draig.lan (localhost [IPv6:::1])\n by draig.lan (Postfix) with ESMTP id 6134E616F5;\n Wed, 22 Apr 2026 13:52:53 +0100 (BST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776863326; x=1777468126; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=gSYzG4w2krdb3nT01JqHA9xtpgh1UWf3StMYQUTc4bg=;\n b=HtVBWNOO96q+xrM2xah91EcqK+k2B328tiMKgHjSnWagHDg9t44KG9bptzcsQIYiWY\n +L3QhgFK9NQbGFUSm5XZw2U2doIQYpegO929qntrNwoHQSNQhMLOJGMT6D28eiJsxQRp\n 18q4WcvksRcItIVGD0fPrAjyhKirNaSefQhbG70svvcxxU7hkuOoFg3pMMu0VdIs+gzY\n Jl91j4712owMRPkUoyaOglQ4jMlaVMKRy9jXBeN7vWoLwV1BITHjeYdae3iDVsN9GHrk\n 1sG+84pq3rZlUxNbQRQ+zGph4bo5QIuZxBHVj0OvTfYdZ4kRA1gGwdaoQ8PeU5Fgw94e\n NOaw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776863326; x=1777468126;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=gSYzG4w2krdb3nT01JqHA9xtpgh1UWf3StMYQUTc4bg=;\n b=Rup7oTYGqLgWnrS7YmHOsuoLfM7FCYLOU8scCOMdKsoH+38x1itwblQyG2GcDfwG/Z\n q1uzbZ8a77NUZUiZWWv9XMuCYvQ9TpPA2EBWIPAEqZZ9FMj/VSN1X/l3EWzxmPJVkydJ\n EUzhiNB57tqeqpfZx/lK6hHKeW4YCBPVxMqF5o+Piy1myuk3Gw7vwzUObLoG31M2wcgm\n X0VpHt93WSqVRUqYdL6qa6EwH5MQZ+IN48gSmZkKxAZACIvF+xGq7tEXdcCPQQLQ5Tav\n IOqJryj+YcyFWyy7zY8JRWEaGVhrb2YMBEV6Sn5lEbrwnCHaFnOkVZNk8JvH3SY90CJ8\n XX/g==","X-Gm-Message-State":"AOJu0YxH8oZK05PjOf+Mcvq130lsHxF3DGK+0dOXd87BDjOEPu2L3Dz4\n Y1U7uPPtRam+RdLKpf1Ul1QcuJK9qjVxBdbdP4GoyUH1HFP0iHEpGeYVBskXt7k43gHOGwnOuoJ\n GoP/tS3A=","X-Gm-Gg":"AeBDiet+Lua4AHyvdQRgRNL1DxMSYOX5RllsMt92roKp4lbcujmPzIF3SEXN4J7Xn1B\n oVB2whk+SCJYv1u+ChrD6MWL8yK0oTaY1YHQe6QiqpJjqfbbq0xXKGwWx/APQ00j+FB2WxNAh9N\n /y+QMT1oVk8bVmKjz0dlLhczPmLOL3BeJBlOcElPXD2b+T53POXolG4cSj6tRNqaHLAAdSuuHEA\n SP1muJNViFtLBi0oCoftSgy8qpBVfLrFXGe4t/MxEppWkRKz2lv/M5yVPtDNCTTt4eaaUF0XYil\n KtqEnv9ZphtXPkrBDEmzSeKDo4KyXHRh3xDErkUuu85iWuWmCmZuAEIivaKRrvKoUrVguHWExgM\n 7RPGDIXCCUac+LD+aa8szxfvKxsrVd3qvz+HWjQXd/27O5ytidJI/L9ZJUEpnmffGXQUcjJiE6y\n i5SVEreONLm/wGnHpmaDGWefrvdGmg394pMerdIMFap9qs","X-Received":"by 2002:a17:907:25cd:b0:ba9:559:10c8 with SMTP id\n a640c23a62f3a-ba905591bf7mr529933866b.41.1776862953878;\n Wed, 22 Apr 2026 06:02:33 -0700 (PDT)","From":"=?utf-8?q?Alex_Benn=C3=A9e?= ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , Alexander Graf ,\n Peter Maydell ,\n Paolo Bonzini ,\n Mohamed Mediouni , kvm@vger.kernel.org,\n qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= ","Subject":"[PATCH v3 29/32] target/arm: implement global monitor events","Date":"Wed, 22 Apr 2026 13:52:46 +0100","Message-ID":"<20260422125250.1303100-30-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260422125250.1303100-1-alex.bennee@linaro.org>","References":"<20260422125250.1303100-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::22d;\n envelope-from=alex.bennee@linaro.org; helo=mail-lj1-x22d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Moving from Exclusive to Open Access should generate event stream\nevents. Technically a non-exclusive store to any address range covered\nby the global monitor should also trigger such an event but we can\nonly detect that after the event by seeing if memory doesn't match\ncpu_exclusive_val when processing the eventual store exclusive.\n\nThe CLREX instruction has the same effect as do other operations\nclearing the exclusive state (such as eret).\n\nWe special case STLR/STL (Store Release) instructions to generate\nevents because their use is a suggested pattern for clearing locks\nthat might be sleeping. We only trigger the event if we detect an\nexclusive instruction is running.\n\nSigned-off-by: Alex Bennée \n\n---\nv2\n - add gen_global_event_reg() and use that\n - add handling for STL/STLR\n---\n target/arm/internals.h | 1 +\n target/arm/tcg/translate.h | 14 ++++++++++++++\n target/arm/tcg/translate-a64.c | 23 +++++++++++++++++++++++\n target/arm/tcg/translate.c | 20 ++++++++++++++++++++\n 4 files changed, 58 insertions(+)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 089f679ac0a..7045b4a56bd 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -709,6 +709,7 @@ static inline void arm_broadcast_event(void)\n static inline void arm_clear_exclusive(CPUARMState *env)\n {\n env->exclusive_addr = -1;\n+ arm_broadcast_event();\n }\n \n /**\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 9bf2701a56b..01053060af4 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -882,6 +882,20 @@ static inline void gen_event_reg(void)\n #endif\n }\n \n+/*\n+ * Some events affect all PEs in the same shareability domain. In\n+ * practice as we currently model SMP systems as single SoC devices so\n+ * we signal them all.\n+ */\n+static inline void gen_global_event_reg(void)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ /* re-use the SEV helper */\n+ gen_helper_sev(tcg_env);\n+#endif\n+}\n+\n+\n /*\n * Helpers for implementing sets of trans_* functions.\n * Defer the implementation of NAME to FUNC, with optional extra arguments.\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex f30df5dbfed..a1b0cc9508e 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -2253,6 +2253,7 @@ static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a)\n static bool trans_CLREX(DisasContext *s, arg_CLREX *a)\n {\n tcg_gen_movi_i64(cpu_exclusive_addr, -1);\n+ gen_global_event_reg();\n return true;\n }\n \n@@ -3407,6 +3408,14 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);\n }\n tcg_gen_mov_i64(cpu_reg(s, rd), tmp);\n+\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n+\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -3544,6 +3553,7 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n TCGv_i64 clean_addr;\n MemOp memop;\n bool iss_sf = ldst_iss_sf(a->sz, false, false);\n+ TCGLabel *skip_monitor_event = gen_new_label();\n \n /*\n * StoreLORelease is the same as Store-Release for QEMU, but\n@@ -3562,6 +3572,19 @@ static bool trans_STLR(DisasContext *s, arg_stlr *a)\n true, a->rn != 31, memop);\n do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,\n iss_sf, a->lasr);\n+\n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STLR to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 59925151fc3..18d64620e40 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -2116,6 +2116,12 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,\n tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2);\n }\n tcg_gen_mov_i32(cpu_R[rd], t0);\n+ /*\n+ * On a successful StoreExcl the global monitor transitions from\n+ * Exclusive to Open Access and at that point generate an Event\n+ * for PEs in the same memory sharing domain.\n+ */\n+ gen_global_event_reg();\n tcg_gen_br(done_label);\n \n gen_set_label(fail_label);\n@@ -4218,6 +4224,7 @@ static bool trans_STLEXH(DisasContext *s, arg_STREX *a)\n static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n {\n TCGv_i32 addr, tmp;\n+ TCGLabel *skip_monitor_event;\n \n if (!ENABLE_ARCH_8) {\n return false;\n@@ -4230,10 +4237,23 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)\n \n addr = load_reg(s, a->rn);\n tmp = load_reg(s, a->rt);\n+ skip_monitor_event = gen_new_label();\n tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);\n gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);\n disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);\n \n+ /*\n+ * We don't fully model the global monitor as it would be very\n+ * expensive for every memory access. However in the Arm ARM \"Use\n+ * of Wait for Event (WFE) and Send Event (SEV) with lock\" it does\n+ * give the example of using STL to clear a lock. So if a lock is\n+ * active trigger the global event register so we don't deadlock\n+ * while sleeping.\n+ */\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, cpu_exclusive_addr, -1, skip_monitor_event);\n+ gen_global_event_reg();\n+ gen_set_label(skip_monitor_event);\n+\n return true;\n }\n \n","prefixes":["v3","29/32"]}