{"id":2226477,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226477/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-26-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-26-alex.bennee@linaro.org>","date":"2026-04-22T12:52:42","name":"[v3,25/32] target/arm: redefine event stream fields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2d2d112c144c23fd5bcb0db2a2be699772b724af","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-26-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226477/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226477/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gWwpYdgC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The event stream control bits are the same for both CNTHCTL and\nCNTKCTL so rather than duplicating the definitions rename them to be\nuseful in both cases.\n\nWe will need these in a later commit when we start implementing event\nstreams.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n---\n target/arm/internals.h | 11 +++++++----\n target/arm/helper.c | 8 ++++----\n 2 files changed, 11 insertions(+), 8 deletions(-)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 85980f0e69a..dc593f1fec8 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -263,14 +263,17 @@ FIELD(VSTCR, SA, 30, 1)\n * have different bit definitions, and EL1PCTEN might be\n * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to\n * disambiguate if necessary.\n+ *\n+ * The event stream bits (EVN*) are in the same position for\n+ * CNTKCTL_EL1/CTNKCTL.\n */\n FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)\n FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)\n FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)\n FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)\n-FIELD(CNTHCTL, EVNTEN, 2, 1)\n-FIELD(CNTHCTL, EVNTDIR, 3, 1)\n-FIELD(CNTHCTL, EVNTI, 4, 4)\n+FIELD(CNTxCTL, EVNTEN, 2, 1)\n+FIELD(CNTxCTL, EVNTDIR, 3, 1)\n+FIELD(CNTxCTL, EVNTI, 4, 4)\n FIELD(CNTHCTL, EL0VTEN, 8, 1)\n FIELD(CNTHCTL, EL0PTEN, 9, 1)\n FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)\n@@ -280,7 +283,7 @@ FIELD(CNTHCTL, EL1TVT, 13, 1)\n FIELD(CNTHCTL, EL1TVCT, 14, 1)\n FIELD(CNTHCTL, EL1NVPCT, 15, 1)\n FIELD(CNTHCTL, EL1NVVCT, 16, 1)\n-FIELD(CNTHCTL, EVNTIS, 17, 1)\n+FIELD(CNTxCTL, EVNTIS, 17, 1)\n FIELD(CNTHCTL, CNTVMASK, 18, 1)\n FIELD(CNTHCTL, CNTPMASK, 19, 1)\n \ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 40dd070d2c1..81a07ca42d0 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -1746,9 +1746,9 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint32_t valid_mask =\n R_CNTHCTL_EL0PCTEN_E2H1_MASK |\n R_CNTHCTL_EL0VCTEN_E2H1_MASK |\n- R_CNTHCTL_EVNTEN_MASK |\n- R_CNTHCTL_EVNTDIR_MASK |\n- R_CNTHCTL_EVNTI_MASK |\n+ R_CNTxCTL_EVNTEN_MASK |\n+ R_CNTxCTL_EVNTDIR_MASK |\n+ R_CNTxCTL_EVNTI_MASK |\n R_CNTHCTL_EL0VTEN_MASK |\n R_CNTHCTL_EL0PTEN_MASK |\n R_CNTHCTL_EL1PCTEN_E2H1_MASK |\n@@ -1763,7 +1763,7 @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,\n R_CNTHCTL_EL1TVCT_MASK |\n R_CNTHCTL_EL1NVPCT_MASK |\n R_CNTHCTL_EL1NVVCT_MASK |\n- R_CNTHCTL_EVNTIS_MASK;\n+ R_CNTxCTL_EVNTIS_MASK;\n }\n if (cpu_isar_feature(aa64_ecv, cpu)) {\n valid_mask |= R_CNTHCTL_ECV_MASK;\n","prefixes":["v3","25/32"]}