{"id":2226476,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226476/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-31-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-31-alex.bennee@linaro.org>","date":"2026-04-22T12:52:47","name":"[v3,30/32] target/arm: enable event stream on WFE instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c02e8b0513d3e53c1058a1d40be3d769c991b2a2","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-31-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226476/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226476/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=JQlBh8ik;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Two generic timers (K and H) are capable of generating timer event\nstream events. Provide a helper to calculate when the nearest one will\nhappen.\n\nNow we can calculate when the next event stream event is we can re-use\nthe wfxt_timer and configure it to fire as we enter a WFE that is\ngoing to sleep. Reverse the M-profile logic so we can enter a sleep\nstate in both profiles.\n\nSigned-off-by: Alex Bennée \n\n---\nv2\n - merged target/arm: add gt_calc_next_event_stream\n - update to use halt_reason\n - made arm_wfxt_timer_cb atomically consume halt_reason\n---\n target/arm/cpu.c | 13 ++++\n target/arm/tcg/op_helper.c | 129 +++++++++++++++++++++++++++++++------\n 2 files changed, 122 insertions(+), 20 deletions(-)","diff":"diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 124be8c401e..7a6ad45ae08 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -799,10 +799,23 @@ bool arm_cpu_exec_halt(CPUState *cs)\n }\n #endif\n \n+/*\n+ * Unlike almost everything else that messes with the halt_reason and\n+ * event_register details the timer callbacks are not in the vCPU\n+ * context.\n+ *\n+ * To prevent races we atomically consume a HALT_WFE and set the event\n+ * register. Either way we trigger the an exit event.\n+ */\n static void arm_wfxt_timer_cb(void *opaque)\n {\n ARMCPU *cpu = opaque;\n CPUState *cs = CPU(cpu);\n+ CPUARMState *env = &cpu->env;\n+\n+ if (qatomic_cmpxchg(&env->halt_reason, HALT_WFE, NOT_HALTED)) {\n+ qatomic_set(&env->event_register, true);\n+ }\n \n /*\n * We expect the CPU to be halted; this will cause arm_cpu_is_work()\ndiff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c\nindex 6a2be85fcaa..030209360e8 100644\n--- a/target/arm/tcg/op_helper.c\n+++ b/target/arm/tcg/op_helper.c\n@@ -477,6 +477,97 @@ void HELPER(sev)(CPUARMState *env)\n arm_broadcast_event();\n }\n \n+#ifndef CONFIG_USER_ONLY\n+/*\n+ * Event Stream events don't do anything apart from wake up sleeping\n+ * cores. These helpers calculate the next event stream event time so\n+ * the WFE helper can decide when its next wake up tick will be.\n+ */\n+static int64_t gt_recalc_one_evt(CPUARMState *env, uint32_t control, uint64_t offset)\n+{\n+ ARMCPU *cpu = env_archcpu(env);\n+ bool evnten = FIELD_EX32(control, CNTxCTL, EVNTEN);\n+\n+ if (evnten) {\n+ int evnti = FIELD_EX32(control, CNTxCTL, EVNTI);\n+ bool evntis = FIELD_EX32(control, CNTxCTL, EVNTIS);\n+ bool evntdir = FIELD_EX32(control, CNTxCTL, EVNTDIR);\n+ /*\n+ * To figure out when the next event timer should fire we need\n+ * to calculate which bit of the counter we want to flip and\n+ * which transition counts.\n+ *\n+ * So we calculate 1 << bit - current lower bits and then add\n+ * 1 << bit if the bit needs to flip twice to meet evntdir\n+ */\n+ int bit = evntis ? evnti + 8 : evnti;\n+ uint64_t count = gt_get_countervalue(env) - offset;\n+ uint64_t target_bit = BIT_ULL(bit);\n+ uint64_t lower_bits = MAKE_64BIT_MASK(0, bit - 1);\n+ uint64_t next_tick = target_bit - (count & lower_bits);\n+ uint64_t abstick;\n+\n+ /* do we need to bit flip twice? */\n+ if (((count & target_bit) != 0) ^ evntdir) {\n+ next_tick += target_bit;\n+ }\n+\n+ /*\n+ * Note that the desired next expiry time might be beyond the\n+ * signed-64-bit range of a QEMUTimer -- in this case we just\n+ * set the timer for as far in the future as possible. When the\n+ * timer expires we will reset the timer for any remaining period.\n+ */\n+ if (uadd64_overflow(next_tick, offset, &abstick)) {\n+ abstick = UINT64_MAX;\n+ }\n+ if (abstick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {\n+ return INT64_MAX;\n+ } else {\n+ return abstick;\n+ }\n+ }\n+\n+ return -1;\n+}\n+\n+/*\n+ * Calculate the next event stream time and return it. Returns -1 if\n+ * no event streams are enabled. It is up to the WFE helpers to decide\n+ * on the next time.\n+ */\n+static int64_t gt_calc_next_event_stream(CPUARMState *env)\n+{\n+ ARMCPU *cpu = env_archcpu(env);\n+ uint64_t hcr = arm_hcr_el2_eff(env);\n+ int64_t next_time = -1;\n+ uint64_t offset;\n+\n+ /* Unless we are missing EL2 this can generate events */\n+ if (arm_feature(env, ARM_FEATURE_EL2)) {\n+ offset = gt_direct_access_timer_offset(env, GTIMER_PHYS);\n+ next_time = gt_recalc_one_evt(env, env->cp15.cnthctl_el2, offset);\n+ }\n+\n+ /* Event stream events from virtual counter enabled? */\n+ if (!cpu_isar_feature(aa64_vh, cpu) ||\n+ !((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE))) {\n+ int64_t next_virt_time;\n+ offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);\n+ next_virt_time = gt_recalc_one_evt(env, env->cp15.c14_cntkctl, offset);\n+\n+ /* is this earlier than the next physical event? */\n+ if (next_virt_time > 0) {\n+ if (next_time < 0 || next_virt_time < next_time) {\n+ next_time = next_virt_time;\n+ }\n+ }\n+ }\n+\n+ return next_time;\n+}\n+#endif\n+\n void HELPER(wfe)(CPUARMState *env)\n {\n #ifdef CONFIG_USER_ONLY\n@@ -489,32 +580,30 @@ void HELPER(wfe)(CPUARMState *env)\n #else\n /*\n * WFE (Wait For Event) is a hint instruction.\n- * For Cortex-M (M-profile), we implement the strict architectural behavior:\n+ *\n * 1. Check the Event Register (set by SEV or SEVONPEND).\n * 2. If set, clear it and continue (consume the event).\n */\n- if (arm_feature(env, ARM_FEATURE_M)) {\n- CPUState *cs = env_cpu(env);\n+ CPUState *cs = env_cpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n \n- if (env->event_register) {\n- env->event_register = false;\n- return;\n- }\n+ if (env->event_register) {\n+ env->event_register = false;\n+ return;\n+ }\n \n- env->halt_reason = HALT_WFE;\n- cs->exception_index = EXCP_HLT;\n- cs->halted = 1;\n- cpu_loop_exit(cs);\n- } else {\n- /*\n- * For A-profile and others, we rely on the existing \"yield\" behavior.\n- * Don't actually halt the CPU, just yield back to top\n- * level loop. This is not going into a \"low power state\"\n- * (ie halting until some event occurs), so we never take\n- * a configurable trap to a different exception level\n- */\n- HELPER(yield)(env);\n+ /* For A-profile we also can be woken by the event stream */\n+ if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu->wfxt_timer) {\n+ int64_t next_event = gt_calc_next_event_stream(env);\n+ if (next_event > 0) {\n+ timer_mod(cpu->wfxt_timer, next_event);\n+ }\n }\n+\n+ env->halt_reason = HALT_WFE;\n+ cs->exception_index = EXCP_HLT;\n+ cs->halted = 1;\n+ cpu_loop_exit(cs);\n #endif\n }\n \n","prefixes":["v3","30/32"]}