{"id":2226469,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226469/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-2-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-2-alex.bennee@linaro.org>","date":"2026-04-22T12:52:18","name":"[v3,01/32] target/arm: migrate basic syndrome helpers to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f9342eadedf3a8f3edc93775d672250847f361b0","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-2-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226469/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226469/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=o4fZh02U;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0zk021fQz1yCv\n\tfor ; Wed, 22 Apr 2026 22:56:08 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFX4d-0005vM-73; Wed, 22 Apr 2026 08:52:59 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFX4b-0005uI-QD\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 08:52:57 -0400","from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFX4Z-0005Rb-D5\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 08:52:57 -0400","by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-488a8ca4aadso74083175e9.3\n for ; Wed, 22 Apr 2026 05:52:54 -0700 (PDT)","from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e4ffa8sm46533031f8f.35.2026.04.22.05.52.51\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 22 Apr 2026 05:52:51 -0700 (PDT)","from draig.lan (localhost [IPv6:::1])\n by draig.lan (Postfix) with ESMTP id 0D4535F941;\n Wed, 22 Apr 2026 13:52:51 +0100 (BST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776862374; x=1777467174; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=SFHYYol3fQLtpVQaYQnNjnL8iJcFReh9WH604Hh8s60=;\n b=o4fZh02U3zjneAJDQgLVKFQ59W7HJuxelQWY7bSkZ4l3K3TbS1/HG2/E0Ui/vNiNG6\n uxhXxOCltdpWBXVs3oHmD+qbvkNV+PxUHGSL2u2D8gY9/SyEbs0aHr1UlYS929HRvR/E\n VwdvyUmdTKEMuW/LHUZcZhqRjod7r4NE3jshc803SyFhIzNZkkPjH3JCz/k6GzZ074Se\n S7S7CCWC0357HtV9pFOGXBqHCcoMM2RWsXKBy64VvfiExMDHpKiEx6VsspwIkctocWwg\n 2CHU+Hf0jvi7H0clG9LB6gyOPG87UDCKJTMc812IpvY6om3JzwSWdqZXufUnXKq4hIH3\n +YrA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776862374; x=1777467174;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=SFHYYol3fQLtpVQaYQnNjnL8iJcFReh9WH604Hh8s60=;\n b=cDJWhj+TFEPhs9/lU1g0Q6NZUuqJXtRegKwLwisvoMzvDhtWlzv21zpZ5o44Xil1jJ\n uFB9UOryg4SHLR6gjDcorOBe6bm8ZNzDAmhCHxaezEdAj31KQKk8mJBvBG2XNivaYLEv\n klhAPvhWiLZdpcfmvCoKVwg4rdKPTAPUyDAkw3BW8q9tcPo3++U7j4nRIvQrE2YDQLMJ\n q5Y/bSmvyNjOZ0oZhqD12DrfnUilkwd7zbk2a2FutqtFjqj5m1xXmBOIT8XUhVBe2Ovg\n BRJgPi3pTNzlCTOrkSTQFnsGea9xdxVeWAopyRyV/uEGBkcovaQYnIN0zlXi2lThdzx6\n GAmA==","X-Gm-Message-State":"AOJu0YyjbolfZWmqW6dD0dukAyoiGAmyPGG0W0Etx3qgvWNH/Y7vQdPU\n vLGGMPEvoXfDownCnE9wwONSZRv5FnIg7P1nKpoqNWhgzMBuPvHuqwFBtilKwqiNF+o=","X-Gm-Gg":"AeBDievVhStAKyoPFpT2lVYi56blPfp2yIzRt4ci984lM+rtKcfxyymxNBYAKR3d3JY\n NTLX5Utzn9zMaCyID3h6AvqfV0alf5lnpjCxa7IOoPFtXFFednnEZuK+Qt0XBVNCk85rsjIax25\n NLeDuIWnBgi52LAvHypNt5fD42VCFghNECf4aDlaiI2ui0gULsNfvl+WHo7hRJiIm7y8EcfEQAN\n IgLf3S/VUnxC2BRXU2I/AP3tWGDQtpeAwjN1eKr75qrL985OcAznN77HSFdzVpBZ86HqAvcHqaE\n 1CROdMNL9I5CaiQYBzSkrSd59T0lfPVh8qKcA/sGNZncK0UVHTzbrnwHYIFw+51LRspocJU8D00\n Ueztz1s+9Kmm/kbD+1yaK94mJ0AJZJGhyOu1z+k2FVCveasYm6CyUVRNK0jeSZ5ZpGPUsZ7dTG9\n YkzeaQaztiLoZU80ZZGzLQFYVS61QNrcZ0YA==","X-Received":"by 2002:a05:600c:a107:b0:489:d1c:d468 with SMTP id\n 5b1f17b1804b1-4890d1cdaedmr163029735e9.31.1776862373605;\n Wed, 22 Apr 2026 05:52:53 -0700 (PDT)","From":"=?utf-8?q?Alex_Benn=C3=A9e?= ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , Alexander Graf ,\n Peter Maydell ,\n Paolo Bonzini ,\n Mohamed Mediouni , kvm@vger.kernel.org,\n qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= ,\n Richard Henderson ","Subject":"[PATCH v3 01/32] target/arm: migrate basic syndrome helpers to\n registerfields","Date":"Wed, 22 Apr 2026 13:52:18 +0100","Message-ID":"<20260422125250.1303100-2-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260422125250.1303100-1-alex.bennee@linaro.org>","References":"<20260422125250.1303100-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We have a registerfields interface which we can use for defining\nfields alongside helpers to access them. Define the basic syndrome\nlayout and convert the helpers that take the imm16 data directly.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n---\n target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++-----------\n 1 file changed, 57 insertions(+), 18 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bff61f052cc..517fb2368bc 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -25,7 +25,7 @@\n #ifndef TARGET_ARM_SYNDROME_H\n #define TARGET_ARM_SYNDROME_H\n \n-#include \"qemu/bitops.h\"\n+#include \"hw/core/registerfields.h\"\n \n /* Valid Syndrome Register EC field values */\n enum arm_exception_class {\n@@ -76,6 +76,11 @@ enum arm_exception_class {\n EC_AA64_BKPT = 0x3c,\n };\n \n+/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n+FIELD(SYNDROME, EC, 26, 6)\n+FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, ISS, 0, 25)\n+\n typedef enum {\n SME_ET_AccessTrap,\n SME_ET_Streaming,\n@@ -113,12 +118,12 @@ typedef enum {\n \n static inline uint32_t syn_get_ec(uint32_t syn)\n {\n- return syn >> ARM_EL_EC_SHIFT;\n+ return FIELD_EX32(syn, SYNDROME, EC);\n }\n \n static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n {\n- return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);\n+ return FIELD_DP32(syn, SYNDROME, EC, ec);\n }\n \n /*\n@@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)\n */\n static inline uint32_t syn_uncategorized(void)\n {\n- return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_UNCATEGORIZED);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n+FIELD(ISS_IMM16, IMM16, 0, 16)\n+\n static inline uint32_t syn_aa64_svc(uint32_t imm16)\n {\n- return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_hvc(uint32_t imm16)\n {\n- return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_smc(uint32_t imm16)\n {\n- return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_hvc(uint32_t imm16)\n {\n- return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA32_HVC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_smc(void)\n {\n- return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_AA32_SMC);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n {\n- return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);\n+ uint32_t res = syn_set_ec(0, EC_AA64_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n- return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)\n- | (is_16bit ? 0 : ARM_EL_IL);\n+ uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n+ res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n+ return res;\n }\n \n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n@@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)\n \n static inline uint32_t syn_sve_access_trap(void)\n {\n- return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_SVEACCESSTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n /*\n@@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)\n \n static inline uint32_t syn_illegalstate(void)\n {\n- return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_ILLEGALSTATE);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_pcalignment(void)\n {\n- return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;\n+ uint32_t res = syn_set_ec(0, EC_PCALIGNMENT);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ return res;\n }\n \n static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn)\n@@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn)\n \n static inline uint32_t syn_serror(uint32_t extra)\n {\n- return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;\n+ uint32_t res = syn_set_ec(0, EC_SERROR);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+ res = FIELD_DP32(res, SYNDROME, ISS, extra);\n+ return res;\n }\n \n static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,\n","prefixes":["v3","01/32"]}