{"id":2226457,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226457/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-25-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-25-alex.bennee@linaro.org>","date":"2026-04-22T12:52:41","name":"[v3,24/32] target/arm: teach arm_cpu_has_work about halting reasons","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"84320027a0944765f757e7a3e5cac1a33b7c923f","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-25-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226457/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226457/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=tZ1SOs5f;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::443;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x443.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"With the advent of WFE and WFI we need to pay closer attention to the\nreason why the vCPU may be sleeping to figure out if we should wake\nit up.\n\nCreate env->halt_reason to track this and then re-order the tests so\nwe:\n\n - ignore everything is the vCPU is powered off\n - wake up if the event_register is set and we were in a WFE\n - otherwise any IRQ event does wake the vCPU up.\n\nSigned-off-by: Alex Bennée \n---\n target/arm/cpu.h | 27 +++++++++++++++++++++++++\n target/arm/arm-powerctl.c | 4 +++-\n target/arm/cpu.c | 40 +++++++++++++++++++++++++++-----------\n target/arm/kvm.c | 5 +++--\n target/arm/machine.c | 2 +-\n target/arm/tcg/op_helper.c | 3 +++\n 6 files changed, 66 insertions(+), 15 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 657ff4ab20b..98cdfa6f130 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -257,6 +257,19 @@ typedef enum ARMFPStatusFlavour {\n } ARMFPStatusFlavour;\n #define FPST_COUNT 10\n \n+/**\n+ * ARMHaltReason - the reason we have entered halt state\n+ *\n+ * To be able to correctly wake up via arm_cpu_has_work() we need to\n+ * track the reason we went to sleep.\n+ */\n+typedef enum {\n+ NOT_HALTED = 0,\n+ HALT_PSCI,\n+ HALT_WFI,\n+ HALT_WFE\n+} ARMHaltReason;\n+\n typedef struct CPUArchState {\n /* Regs for current mode. */\n uint32_t regs[16];\n@@ -760,6 +773,9 @@ typedef struct CPUArchState {\n /* Optional fault info across tlb lookup. */\n ARMMMUFaultInfo *tlb_fi;\n \n+ /* Reason the CPU is halted */\n+ ARMHaltReason halt_reason;\n+\n /*\n * The event register is shared by all ARM profiles (A/R/M),\n * so it is stored in the top-level CPU state.\n@@ -1691,6 +1707,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)\n #endif\n }\n \n+/**\n+ * arm_set_cpu_power_state() - set power state synced with halt_reason\n+ */\n+static inline void arm_set_cpu_power_state(ARMCPU *cpu, ARMPSCIState state)\n+{\n+ CPUARMState *env = &cpu->env;\n+\n+ cpu->power_state = state;\n+ env->halt_reason = (state == PSCI_OFF) ? HALT_PSCI : NOT_HALTED;\n+}\n+\n #define HCR_VM (1ULL << 0)\n #define HCR_SWIO (1ULL << 1)\n #define HCR_PTW (1ULL << 2)\ndiff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c\nindex a788376d1d3..4ca63a54443 100644\n--- a/target/arm/arm-powerctl.c\n+++ b/target/arm/arm-powerctl.c\n@@ -78,6 +78,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,\n \n /* Finally set the power status */\n assert(bql_locked());\n+ target_cpu->env.halt_reason = NOT_HALTED;\n target_cpu->power_state = PSCI_ON;\n }\n \n@@ -186,6 +187,7 @@ static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,\n \n /* Finally set the power status */\n assert(bql_locked());\n+ target_cpu->env.halt_reason = NOT_HALTED;\n target_cpu->power_state = PSCI_ON;\n }\n \n@@ -239,7 +241,7 @@ static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,\n ARMCPU *target_cpu = ARM_CPU(target_cpu_state);\n \n assert(bql_locked());\n- target_cpu->power_state = PSCI_OFF;\n+ arm_set_cpu_power_state(target_cpu, PSCI_OFF);\n target_cpu_state->halted = 1;\n target_cpu_state->exception_index = EXCP_HLT;\n }\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex ccc47c8a9ad..124be8c401e 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -144,18 +144,36 @@ static bool arm_cpu_has_work(CPUState *cs)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n \n- if (arm_feature(&cpu->env, ARM_FEATURE_M)) {\n- if (cpu->env.event_register) {\n- return true;\n- }\n+ /*\n+ * Only another PSCI call can wake the CPU up in which case the\n+ * power_state would be set by arm_set_cpu_on_and_reset_async_work()\n+ */\n+ if (cpu->power_state == PSCI_OFF) {\n+ g_assert(cpu->env.halt_reason == HALT_PSCI);\n+ return false;\n+ }\n+\n+ /*\n+ * A wake-up event should only wake us if we are halted on a WFE\n+ */\n+ if (cpu->env.halt_reason == HALT_WFE && cpu->env.event_register) {\n+ cpu->env.halt_reason = NOT_HALTED;\n+ return true;\n+ }\n+\n+ /*\n+ * Otherwise pretty much any IRQ would wake us up\n+ */\n+ if (cpu_test_interrupt(cs,\n+ CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD\n+ | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI\n+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR\n+ | CPU_INTERRUPT_EXITTB)) {\n+ cpu->env.halt_reason = NOT_HALTED;\n+ return true;\n }\n \n- return (cpu->power_state != PSCI_OFF)\n- && cpu_test_interrupt(cs,\n- CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD\n- | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI\n- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR\n- | CPU_INTERRUPT_EXITTB);\n+ return false;\n }\n #endif /* !CONFIG_USER_ONLY */\n \n@@ -250,7 +268,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)\n env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;\n env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;\n \n- cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;\n+ arm_set_cpu_power_state(cpu, cs->start_powered_off ? PSCI_OFF : PSCI_ON);\n \n if (arm_feature(env, ARM_FEATURE_AARCH64)) {\n /* 64 bit CPUs always start in 64 bit mode */\ndiff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex d4a68874b88..c08e4797b32 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -1143,11 +1143,12 @@ static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)\n if (cap_has_mp_state) {\n struct kvm_mp_state mp_state;\n int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);\n+ ARMPSCIState state;\n if (ret) {\n return ret;\n }\n- cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ?\n- PSCI_OFF : PSCI_ON;\n+ state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? PSCI_OFF : PSCI_ON;\n+ arm_set_cpu_power_state(cpu, state);\n }\n return 0;\n }\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex b0e499515cf..62401c5a3ea 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -916,7 +916,7 @@ static int get_power(QEMUFile *f, void *opaque, size_t size,\n {\n ARMCPU *cpu = opaque;\n bool powered_off = qemu_get_byte(f);\n- cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON;\n+ arm_set_cpu_power_state(cpu, powered_off ? PSCI_OFF : PSCI_ON);\n return 0;\n }\n \ndiff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c\nindex 652611b4313..46c745077d5 100644\n--- a/target/arm/tcg/op_helper.c\n+++ b/target/arm/tcg/op_helper.c\n@@ -403,6 +403,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)\n target_el);\n }\n \n+ env->halt_reason = HALT_WFI;\n cs->exception_index = EXCP_HLT;\n cs->halted = 1;\n cpu_loop_exit(cs);\n@@ -464,6 +465,7 @@ void HELPER(wfit)(CPUARMState *env, uint32_t rd)\n } else {\n timer_mod(cpu->wfxt_timer, nexttick);\n }\n+ env->halt_reason = HALT_WFI;\n cs->exception_index = EXCP_HLT;\n cs->halted = 1;\n cpu_loop_exit(cs);\n@@ -508,6 +510,7 @@ void HELPER(wfe)(CPUARMState *env)\n return;\n }\n \n+ env->halt_reason = HALT_WFE;\n cs->exception_index = EXCP_HLT;\n cs->halted = 1;\n cpu_loop_exit(cs);\n","prefixes":["v3","24/32"]}