{"id":2226452,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2226452/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-3-alex.bennee@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260422125250.1303100-3-alex.bennee@linaro.org>","date":"2026-04-22T12:52:19","name":"[v3,02/32] target/arm: migrate system/cp trap syndromes to registerfields","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"92f63a4c513623fd558f583e71201abedb65dd8a","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/1.1/people/39532/?format=json","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-3-alex.bennee@linaro.org/mbox/","series":[{"id":501008,"url":"http://patchwork.ozlabs.org/api/1.1/series/501008/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008","date":"2026-04-22T12:52:20","name":"target/arm: fully model WFxT instructions for A-profile","version":3,"mbox":"http://patchwork.ozlabs.org/series/501008/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2226452/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2226452/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=yO/e00GZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0zgj588nz1yD5\n\tfor ; Wed, 22 Apr 2026 22:54:09 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFX4f-0005x1-83; Wed, 22 Apr 2026 08:53:01 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFX4d-0005vB-0y\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 08:52:59 -0400","from mail-wm1-x335.google.com ([2a00:1450:4864:20::335])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFX4a-0005S6-Jm\n for qemu-devel@nongnu.org; Wed, 22 Apr 2026 08:52:58 -0400","by mail-wm1-x335.google.com with SMTP id\n 5b1f17b1804b1-4891c0620bcso29155925e9.1\n for ; Wed, 22 Apr 2026 05:52:56 -0700 (PDT)","from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488fb7a0c13sm141522075e9.21.2026.04.22.05.52.51\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 22 Apr 2026 05:52:52 -0700 (PDT)","from draig.lan (localhost [IPv6:::1])\n by draig.lan (Postfix) with ESMTP id 209F25F943;\n Wed, 22 Apr 2026 13:52:51 +0100 (BST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776862375; x=1777467175; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=FHkkfCdnBgFoOnCKUMnFf3OjHIWwkdSWF2yGrdtfKkY=;\n b=yO/e00GZg7r/8esw6MjD9yutG0EYh+bq1yJCnZeMVvLU/zwxxCbrr+Ur00Knggl3KS\n FhFFyuwAPloEe7TYX64e/9jJDbUSvYWfsoSE9y0B/drrkUMnDr2PJkkffTmIY7B9rN/q\n aLA6AeeEB9zl+lPPSac0Z64hQ+y/5Q4nO3SDDbhq7rxNvt042DtMH78PRv+dt6c5NMd/\n F2F5L6Syui7/OCIy9Q9EB9+AajRNh+j5gtthA7bKkTjiueqhYp0hNLetZcxlApV0xkiU\n aeaeUHiof5HNRlv7v2bLGw1cNl7ocKLGyrGIjRL4wOGZhdHMcxCOMSAwpbiyBPXQ3G2d\n jCcQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776862375; x=1777467175;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=FHkkfCdnBgFoOnCKUMnFf3OjHIWwkdSWF2yGrdtfKkY=;\n b=RX0KMd44801sa8kLQSAfe/IbIYf1pGVHFZ42ob8yoMvDgSGeHcxiMwiMD3JBwlXpac\n vh8gLZJe+AtxPa58+El0E8JOaJJmgK7/SGySl9d/hC07PXOSZQ7COu+33s5se3GblHYc\n LvqsdYb/LKjk7tgm/vjh1nSCQWPfSxmNvXTcI0ZUWpbxmqa08xMqSnewh6ipPHhiMfO1\n 8Iu7fgPbq/RZJ1W9V8GZK8iSvYdlgXgfLfpvyblo8sIatrP55giRuSBUMLAvM1cGH4EM\n 2sK6PKMNlVLVL38D3IK7aqIAAF58zh+bY1csNI9QEo48Jhi58MX/0y1+Bu2ZInVVWkJd\n BZJg==","X-Gm-Message-State":"AOJu0YwvWL4+z7/3Rm+iX4o4K1jZsSN+GUuO6p3zvbMvgIzcVwgLepBI\n VWcLNBXGXHZRyVH3Do4EccSWyVILHZHcEvcd91a/sC6DqvV9fN54L+Y0goZCrQz8XbgVEK8B4F3\n 1E9NspnA=","X-Gm-Gg":"AeBDieuHOzN5OrxwigmRoVzGUP1Tww9u9LJipb2hP4T6svjfEy2lodOQUVA5WG6odM6\n 28/cD8SIYejgjGOh2++On8cdlIo54vDYjDuJAeR8J4TfoMny3Zri5JqDnZGvBT2gRi/GzG8/klr\n sxMchcnyAGHw4/5m8l55ECUbm5HTl/68Ep3tsyAG5Y3WMdNuQqBMkuJsijndCzV60AJPNqcJHXW\n 9ffeOJaMY70V9czHpGVw+sY9pFBQx7i3HE4nM4vWuf8UWdet5xu0R3+nwDs5E+4itJhICw7CqE6\n 9oOmGPigVO4Jc3mCTKlQNfS+CwAslfb5by/ZfGpZJiVT9LjPgkNAabAIAVVaA5aY9UXVpLj2TBi\n uKt2yNcqC0GvpTIlyrwL5YBl5J1zZnqx7dwxigbrBg/NS2xeKMhqWG3wKqXDhOzehX4+LE4m3mZ\n 7OcS8tPyZdBfRHwVJalmrXLD7p/2co8we9CA==","X-Received":"by 2002:a05:600c:8284:b0:489:1f3e:5f69 with SMTP id\n 5b1f17b1804b1-4891f3e629bmr167354805e9.18.1776862374998;\n Wed, 22 Apr 2026 05:52:54 -0700 (PDT)","From":"=?utf-8?q?Alex_Benn=C3=A9e?= ","To":"qemu-devel@nongnu.org","Cc":"Pedro Barbuda , Alexander Graf ,\n Peter Maydell ,\n Paolo Bonzini ,\n Mohamed Mediouni , kvm@vger.kernel.org,\n qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= ,\n Richard Henderson ","Subject":"[PATCH v3 02/32] target/arm: migrate system/cp trap syndromes to\n registerfields","Date":"Wed, 22 Apr 2026 13:52:19 +0100","Message-ID":"<20260422125250.1303100-3-alex.bennee@linaro.org>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260422125250.1303100-1-alex.bennee@linaro.org>","References":"<20260422125250.1303100-1-alex.bennee@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::335;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Migrate syn_aa64_sysregtrap and co-processor register trap syndromes\nto the registerfields API. The co-processor syndromes are split\nbetween single and duel register moves.\n\nReviewed-by: Richard Henderson \nSigned-off-by: Alex Bennée \n\n---\nv2\n - use !is_16bit directly\n---\n target/arm/syndrome.h | 124 ++++++++++++++++++++++++++++++++++--------\n 1 file changed, 102 insertions(+), 22 deletions(-)","diff":"diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex 517fb2368bc..29462aa103c 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -78,7 +78,7 @@ enum arm_exception_class {\n \n /* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */\n FIELD(SYNDROME, EC, 26, 6)\n-FIELD(SYNDROME, IL, 25, 1)\n+FIELD(SYNDROME, IL, 25, 1) /* IL=1 for 32 bit instructions */\n FIELD(SYNDROME, ISS, 0, 25)\n \n typedef enum {\n@@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16)\n static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_SVC);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n@@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16)\n static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)\n {\n uint32_t res = syn_set_ec(0, EC_AA32_BKPT);\n- res = FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n res = FIELD_DP32(res, ISS_IMM16, IMM16, imm16);\n return res;\n }\n \n+/*\n+ * ISS encoding for an exception from MSR, MRS, or System instruction\n+ * in AArch64 state.\n+ */\n+FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */\n+FIELD(SYSREG_ISS, CRM, 1, 4)\n+FIELD(SYSREG_ISS, RT, 5, 5)\n+FIELD(SYSREG_ISS, CRN, 10, 4)\n+FIELD(SYSREG_ISS, OP1, 14, 3)\n+FIELD(SYSREG_ISS, OP2, 17, 3)\n+FIELD(SYSREG_ISS, OP0, 20, 2)\n+\n static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,\n int crn, int crm, int rt,\n int isread)\n {\n- return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL\n- | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)\n- | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_SYSTEMREGISTERTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, 1);\n+\n+ res = FIELD_DP32(res, SYSREG_ISS, OP0, op0);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP2, op2);\n+ res = FIELD_DP32(res, SYSREG_ISS, OP1, op1);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRN, crn);\n+ res = FIELD_DP32(res, SYSREG_ISS, RT, rt);\n+ res = FIELD_DP32(res, SYSREG_ISS, CRM, crm);\n+ res = FIELD_DP32(res, SYSREG_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCR or MRC access\n+ * (move to/from co-processor)\n+ */\n+FIELD(COPROC_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_ISS, CRM, 1, 4)\n+FIELD(COPROC_ISS, RT, 5, 5)\n+FIELD(COPROC_ISS, CRN, 10, 4)\n+FIELD(COPROC_ISS, OP1, 14, 3)\n+FIELD(COPROC_ISS, OP2, 17, 3)\n+FIELD(COPROC_ISS, COND, 20, 4)\n+FIELD(COPROC_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,\n int crn, int crm, int rt, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)\n- | (crn << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_ISS, OP2, opc2);\n+ res = FIELD_DP32(res, COPROC_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_ISS, CRN, crn);\n+ res = FIELD_DP32(res, COPROC_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n+/*\n+ * ISS encoding for an exception from an MCRR or MRRC access\n+ * (move to/from co-processor with 2 regs)\n+ */\n+FIELD(COPROC_R2_ISS, ISREAD, 0, 1)\n+FIELD(COPROC_R2_ISS, CRM, 1, 4)\n+FIELD(COPROC_R2_ISS, RT, 5, 5)\n+FIELD(COPROC_R2_ISS, RT2, 10, 5)\n+FIELD(COPROC_R2_ISS, OP1, 16, 4)\n+FIELD(COPROC_R2_ISS, COND, 20, 4)\n+FIELD(COPROC_R2_ISS, CV, 24, 1)\n+\n static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP14RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,\n int rt, int rt2, int isread,\n bool is_16bit)\n {\n- return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)\n- | (is_16bit ? 0 : ARM_EL_IL)\n- | (cv << 24) | (cond << 20) | (opc1 << 16)\n- | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;\n+ uint32_t res = syn_set_ec(0, EC_CP15RRTTRAP);\n+ res = FIELD_DP32(res, SYNDROME, IL, !is_16bit);\n+\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CV, cv);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, COND, cond);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, RT, rt);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, CRM, crm);\n+ res = FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread);\n+\n+ return res;\n }\n \n static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,\n","prefixes":["v3","02/32"]}