{"id":2225940,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225940/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260421203856.3539186-1-bwicaksono@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260421203856.3539186-1-bwicaksono@nvidia.com>","date":"2026-04-21T20:38:56","name":"[v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"be084ffa00afa9a18fc67f9c7bc8f54345b15a19","submitter":{"id":83903,"url":"http://patchwork.ozlabs.org/api/1.1/people/83903/?format=json","name":"Besar Wicaksono","email":"bwicaksono@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260421203856.3539186-1-bwicaksono@nvidia.com/mbox/","series":[{"id":500891,"url":"http://patchwork.ozlabs.org/api/1.1/series/500891/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500891","date":"2026-04-21T20:38:56","name":"[v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","version":2,"mbox":"http://patchwork.ozlabs.org/series/500891/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225940/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225940/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=oRNR9hgB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Add a MIDR range entry and\nrefuse PMCCNTR_EL0 for cycle events on affected parts so\nperf does not mix the two behaviors.\n\nSigned-off-by: Besar Wicaksono \n---\n\nChanges from v1:\n * add CONFIG_ARM64 check to fix build error found by kernel test robot\n * add explicit include of \nv1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-bwicaksono@nvidia.com/\n\n---\n drivers/perf/arm_pmuv3.c | 44 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 44 insertions(+)","diff":"diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\nindex 8014ff766cff..7c39d0804b9f 100644\n--- a/drivers/perf/arm_pmuv3.c\n+++ b/drivers/perf/arm_pmuv3.c\n@@ -8,6 +8,7 @@\n * This code is based heavily on the ARMv7 perf event code.\n */\n \n+#include \n #include \n #include \n #include \n@@ -978,6 +979,41 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,\n \treturn -EAGAIN;\n }\n \n+#ifdef CONFIG_ARM64\n+/*\n+ * List of CPUs that should avoid using PMCCNTR_EL0.\n+ */\n+static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = {\n+\t/*\n+\t * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state.\n+\t * This is an implementation specific behavior and not an erratum.\n+\t *\n+\t * From ARM DDI0487 D14.4:\n+\t * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count\n+\t * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n+\t *\n+\t * From ARM DDI0487 D24.5.2:\n+\t * All counters are subject to any changes in clock frequency, including\n+\t * clock stopping caused by the WFI and WFE instructions.\n+\t * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n+\t * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and\n+\t * WFE instructions.\n+\t */\n+\tMIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n+\t{}\n+};\n+\n+static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n+{\n+\treturn is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus);\n+}\n+#else\n+static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n+{\n+\treturn false;\n+}\n+#endif\n+\n static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n \t\t\t\t struct perf_event *event)\n {\n@@ -1011,6 +1047,14 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n \tif (cpu_pmu->has_smt)\n \t\treturn false;\n \n+\t/*\n+\t * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES\n+\t * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to\n+\t * prevent inconsistency in the results.\n+\t */\n+\tif (armv8pmu_is_in_avoid_pmccntr_cpus())\n+\t\treturn false;\n+\n \treturn true;\n }\n \n","prefixes":["v2"]}