{"id":2225421,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225421/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/aebjdP_EoLMddS4Q@cowardly-lion.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"","date":"2026-04-21T02:39:48","name":"GCC 17.0 PowerPC, V6 [PATCH 4/5]: Make the MMA instructions support -mdense-math.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0b1d0c783d6b624aed0af1755bcd60c184dadc85","submitter":{"id":73991,"url":"http://patchwork.ozlabs.org/api/1.1/people/73991/?format=json","name":"Michael Meissner","email":"meissner@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/aebjdP_EoLMddS4Q@cowardly-lion.the-meissners.org/mbox/","series":[{"id":500713,"url":"http://patchwork.ozlabs.org/api/1.1/series/500713/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=500713","date":"2026-04-21T02:39:48","name":"GCC 17.0 PowerPC, V6 [PATCH 4/5]: Make the MMA instructions support -mdense-math.","version":1,"mbox":"http://patchwork.ozlabs.org/series/500713/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225421/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225421/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=SWCwF05G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=SWCwF05G","sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com","sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com","server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.156.1"],"Received":["from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g06652QDMz1yGt\n\tfor ; Tue, 21 Apr 2026 12:40:29 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id AE01A4CD202B\n\tfor ; Tue, 21 Apr 2026 02:40:26 +0000 (GMT)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n [148.163.156.1])\n by sourceware.org (Postfix) with ESMTPS id 5D18C4BA2E23\n for ; Tue, 21 Apr 2026 02:39:55 +0000 (GMT)","from pps.filterd (m0353729.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63KJgpJS1684990; Tue, 21 Apr 2026 02:39:54 GMT","from ppma23.wdc07v.mail.ibm.com\n (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93])\n by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4dm2j6jc7j-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 21 Apr 2026 02:39:54 +0000 (GMT)","from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1])\n by ppma23.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 63L2KZo3001185;\n Tue, 21 Apr 2026 02:39:53 GMT","from smtprelay04.dal12v.mail.ibm.com ([172.16.1.6])\n by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4dmnsgy0au-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 21 Apr 2026 02:39:53 +0000 (GMT)","from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com\n [10.241.53.104])\n by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 63L2do5E25952964\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Tue, 21 Apr 2026 02:39:50 GMT","from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 3B4A158070;\n Tue, 21 Apr 2026 02:39:50 +0000 (GMT)","from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 85E5558056;\n Tue, 21 Apr 2026 02:39:49 +0000 (GMT)","from cowardly-lion.the-meissners.org (unknown [9.61.149.99])\n by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTPS;\n Tue, 21 Apr 2026 02:39:49 +0000 (GMT)"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org AE01A4CD202B","OpenDKIM Filter v2.11.0 sourceware.org 5D18C4BA2E23"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 5D18C4BA2E23","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org 5D18C4BA2E23","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776739195; cv=none;\n b=HXBZalbRFxSq/NLn/HN7m/xA08K+rhXPKmC0J8dZnidgc0l0AT5EnRpHkiDxL421jyn8ZWG1xZCZ7+tYPbIf56uRL3i6E6h+1u4blAvaHIHuofDV67Hc3VNLJrOPGdI/R5kZag1eoNZXNFONVhsgqHNa8RJfuYuDOVrSx4Sk4TQ=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776739195; c=relaxed/simple;\n bh=/kOb7nuK3vhyHrNLjYEKbE7SjfKKP8Ea9DuUPvpn1Zc=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=FAlGFyCb1RsMDwnMxI0/n9CI1FdeC8Hze4Fnnmmqqv0VMbUHZIJsWTCLanYQlK1tnRFs3786GU2rWPofbjpE40oh6BUF+2PyErsOVPforZEY+6uuO65wo2nmAqwQGgulxaTEVwp1NtbLJ+dEXY4GpEo5yzLDF7gHEYCDzvbuSDM=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=bZdg5RjY/Fuy3A625W5/LTn+kJfS1h\n QmFiw9Tf0nPWA=; b=SWCwF05G6qsq9jdL1k7yExRC5v4Qqx5pDEF13IMPoxsvdD\n mVItKuKLRabclyTdh79j/ZbhrdxuTXpOA8n2CHFlmXCzczQN+Uf0d0LCKxP26Txf\n JssZAJRyvNd2Pv6iLOaWSvQL28cDCdUy6b2VPJ01vtASHvkL9gTQRR0DNX6RJYHa\n 6LtqpwJnoPmNemt3yz8PR/M/63eqkRJ5K3LYWdt8me6orsERTIWwXuHvv5T8JBMn\n gasozJpv3cKNSAO/3RbTmmy8agSOsESR6a6bPkDI9vHpEsB5CYIIy3KA1HpZ2hre\n S3CtSo2kIWp291XXAK6wkni2z35txJQHW+IO7wug==","Date":"Mon, 20 Apr 2026 22:39:48 -0400","From":"Michael Meissner ","To":"Michael Meissner , gcc-patches@gcc.gnu.org,\n Segher Boessenkool ,\n jeevitha ,\n Surya Kumari Jangala ,\n Kishan Parmar ,\n Avinash Jayakar ,\n Ayappan Perumal ,\n Juergen Christ ","Subject":"GCC 17.0 PowerPC, V6 [PATCH 4/5]: Make the MMA instructions support\n -mdense-math.","Message-ID":"","Mail-Followup-To":"Michael Meissner ,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool ,\n jeevitha ,\n Surya Kumari Jangala ,\n Kishan Parmar ,\n Avinash Jayakar ,\n Ayappan Perumal ,\n Juergen Christ ","References":"\n ","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-TM-AS-GCONF":"00","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIxMDAyMSBTYWx0ZWRfX5/YJfQIZPqU3\n uAISl/nUbq05Gw6SYHZpm+CCzZmWZFK7zCeN2bARkTUgmLsS2Ynqtbu5uVxOcd+VT6t9EtiCxA7\n qB5N9C7lHx31DHUOsDg9zxWic6rHm99M2I6Wd4i66WR+ysy3t1VENvbHM+R+inFiOR3i/kCgHdv\n KuggEPixag6eK8ob3ftZQ9AyjjOqmYduyFs76LbGU8p5SRDltZiIK2XVK5C6Nsdm+YcUeJeu2ea\n jErzRJQxqIe7gigdYqQXp4MMCmKbhYlLKaZ407uvOj7YI/vJkljFbIWah85nAIKNWVhkwQjwj6Y\n VekV2dIErkfYsH1OudS9lnimoT5bFRRo4K6wvneqGHS9Wxps1uzH4Si2B2OG+bG8djINw7joS/M\n eCQ79XPKG9y+CDiAln+lg+tueA6NdPbW7EFblyQxfKWci+rthaS6q9a/2lcnBiXTtlThtOnyGyL\n 5oSAtGkcOFCQGcGu0/w==","X-Proofpoint-GUID":"YoMRVI_ir_Wc8B_YZg0VjxQns2oaDPYT","X-Authority-Analysis":"v=2.4 cv=SOJykuvH c=1 sm=1 tr=0 ts=69e6e37a cx=c_pps\n a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=59v-qk_latqwm4fcdJIA:9 a=3ZKOabzyN94A:10 a=CjuIK1q_8ugA:10","X-Proofpoint-ORIG-GUID":"YoMRVI_ir_Wc8B_YZg0VjxQns2oaDPYT","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0\n clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0\n bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604210021","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch completes support for the dense math registes with 512-bit types.\nThe MMA insns have been modfiied to use the 'wD' constraint and the\naccumulator_operand predicate.\n\nThe insn (mma_xxsetaccz) that clears accumulators has been changed to be a\nnormal unspec when -mdense-math. If -mno-dense-math is in effect, the insn\nremains an unspec_volatile due to register constraints and the need to issue a\nde-prime operation.\n\nI added a comment in front of each insn to say which instructions are generated\nby the insns.\n\nI set -mcpu=future to turn on -mdense-math.\n\nI added 2 tests to the testsuite for -mdense-math support.\n\nA future path will add support for 1,024-bit dense registers.\n\nNote, in the intro mail message, I said that this was V4 of the\npatches, but I missed I had submitted V5 on February 21st, 2026, so\nthis is now V6:\n\nThis is version 6 of the patches (which is the same as version 5).\nVersion 5 patches are at:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\ngcc/\n\n2026-04-20 Michael Meissner \n\n\t* config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec.\n\t(mma_xxsetaccz) Convert to being a define_expand that can handle both\n\tthe original MMA support without dense math registers, and support with\n\tdense math register support.\n\t(mma_xxsetaccz_nodm): Rename original mma_xxsetaccz, and restrict this\n\tto when we do not have dense math registers.\n\t(mma_xxsetaccz_dm): New insn for clearing dense math registers.\n\t(mma_): Add support for dense registers.\n\tDocument which instructions are generated by each insn.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do\n\tnot issue a xxmfacc instruction if we support dense math registers.\n\t* config/rs6000/rs6000-cpu.def (FUTURE_MASKS_SERVER): If -mcpu=future,\n\tturn on -mdense-math.\n\t(POWERPC_MASKS): Mark -mdense-math as being set by -mcpu= options.\n\ngcc/testsuite/\n\n2026-04-16 Michael Meissner \n\n\t* gcc.target/powerpc/mma-dm-1.c: New test.\n\t* gcc.target/powerpc/mma-dm-1.c: Likewise.\n\t* lib/target-supports.exp\n\t(check_effective_target_powerpc_dense_math_ok): New powerpc target\n\tsupport.\n---\n gcc/config/rs6000/mma.md | 128 +++++++++++++++-----\n gcc/config/rs6000/rs6000-builtin.cc | 5 +-\n gcc/config/rs6000/rs6000-cpus.def | 2 +\n gcc/testsuite/gcc.target/powerpc/mma-dm-1.c | 67 ++++++++++\n gcc/testsuite/gcc.target/powerpc/mma-dm-2.c | 67 ++++++++++\n gcc/testsuite/lib/target-supports.exp | 19 +++\n 6 files changed, 258 insertions(+), 30 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/mma-dm-1.c\n create mode 100644 gcc/testsuite/gcc.target/powerpc/mma-dm-2.c","diff":"diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex c1e16bf2957..4e7c8b251c9 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -91,6 +91,7 @@ (define_c_enum \"unspec\"\n UNSPEC_MMA_XVI8GER4SPP\n UNSPEC_MMA_XXMFACC\n UNSPEC_MMA_XXMTACC\n+ UNSPEC_MMA_DMSETDMRZ\n ])\n \n (define_c_enum \"unspecv\"\n@@ -530,31 +531,68 @@ (define_insn_and_split \"*mma_disassemble_acc\"\n DONE;\n })\n \n-;; MMA instructions that do not use their accumulators as an input, still\n-;; must not allow their vector operands to overlap the registers used by\n-;; the accumulator. We enforce this by marking the output as early clobber.\n+;; If dense math registers are not available, MMA instructions that do\n+;; not use their accumulators that overlap with FPR registers as an\n+;; input, still must not allow their vector operands to overlap the\n+;; registers used by the accumulator. We enforce this by marking the\n+;; output as early clobber. The prime and de-prime instructions are\n+;; not needed on systems with dense math registers.\n \n (define_insn \"mma_\"\n [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d\")\n \t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0\")]\n \t\t MMA_ACC))]\n- \"TARGET_MMA\"\n+ \"TARGET_MMA_NO_DENSE_MATH\"\n \" %A0\"\n [(set_attr \"type\" \"mma\")])\n \n ;; We can't have integer constants in XOmode so we wrap this in an\n-;; UNSPEC_VOLATILE.\n+;; UNSPEC_VOLATILE. If we have dense math registers, we can just use a normal\n+;; UNSPEC instead of UNSPEC_VOLATILE.\n \n-(define_insn \"mma_xxsetaccz\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=d\")\n+(define_expand \"mma_xxsetaccz\"\n+ [(set (match_operand:XO 0 \"accumulator_operand\")\n \t(unspec_volatile:XO [(const_int 0)]\n \t\t\t UNSPECV_MMA_XXSETACCZ))]\n \"TARGET_MMA\"\n+{\n+ if (TARGET_DENSE_MATH)\n+ {\n+ emit_insn (gen_mma_xxsetaccz_dm (operands[0]));\n+ DONE;\n+ }\n+})\n+\n+;; Clear accumulator without dense math registers\n+(define_insn \"*mma_xxsetaccz_nodm\"\n+ [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=d\")\n+\t(unspec_volatile:XO [(const_int 0)]\n+\t\t\t UNSPECV_MMA_XXSETACCZ))]\n+ \"TARGET_MMA_NO_DENSE_MATH\"\n \"xxsetaccz %A0\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Clear accumulator when dense math registers are available.\n+(define_insn \"mma_xxsetaccz_dm\"\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=wD\")\n+\t(unspec [(const_int 0)]\n+\t\tUNSPEC_MMA_DMSETDMRZ))]\n+ \"TARGET_DENSE_MATH\"\n+ \"dmsetdmrz %A0\"\n+ [(set_attr \"type\" \"mma\")])\n+\n+\f\n+;; MMA operations below. If dense math registers are available, these\n+;; operations will use the 8 accumultors which are separate registers.\n+;; If dense math registers are not available, these operations will use\n+;; accumulators that are overlaid on top of the FPR registers.\n+\n+;; Instructions:\n+;; xvi4ger8 xvi8ger4 xvi16ger2 xvi16ger2s xvf16ger2\n+;; xvbf16ger2 xvf32ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_VV))]\n@@ -562,9 +600,15 @@ (define_insn \"mma_\"\n \" %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instructions:\n+;; xvi4ger8pp xvi8ger4pp xvi8ger4spp xvi16ger2pp xvi16ger2spp\n+;; xvf16ger2pp xvf16ger2pn xvf16ger2np xvf16ger2nn xvbf16ger2pp\n+;; xvbf16ger2pn xvbf16ger2np xvbf16ger2nn xvf32gerpp xvf32gerpn\n+;; xvf32gernp xvf32gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_AVV))]\n@@ -572,8 +616,10 @@ (define_insn \"mma_\"\n \" %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instruction: xvf64ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_PV))]\n@@ -581,9 +627,11 @@ (define_insn \"mma_\"\n \" %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instructions: xvf64gerpp xvf64gerpn xvf64gernp xvf64gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:OO 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_APV))]\n@@ -591,8 +639,10 @@ (define_insn \"mma_\"\n \" %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instruction: pmxvi4ger8\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -604,9 +654,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvi4ger8pp\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -618,8 +670,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions:\n+;; pmxvi16ger2 pmxvi16ger2s pmxvf16ger2 pmxvbf16ger2\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -631,9 +686,14 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions:\n+;; pmxvi16ger2pp pmxvi16ger2spp pmxvf16ger2pp pmxvf16ger2pn\n+;; pmxvf16ger2np pmxvf16ger2nn pmxvbf16ger2pp pmxvbf16ger2pn\n+;; pmxvbf16ger2np pmxvbf16ger2nn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -645,8 +705,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvf32ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -657,9 +719,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvf32gerpp pmxvf32gerpn pmxvf32gernp pmxvf32gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -670,8 +734,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvf64ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -682,9 +748,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvf64gerpp pmxvf64gerpn pmxvf64gernp pmxvf64gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:OO 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -695,8 +763,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvi8ger4\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -708,9 +778,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvi8ger4pp pmxvi8ger4spp\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\ndiff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc\nindex 4d0e541351f..ee4210cc776 100644\n--- a/gcc/config/rs6000/rs6000-builtin.cc\n+++ b/gcc/config/rs6000/rs6000-builtin.cc\n@@ -1130,8 +1130,9 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi,\n \t}\n \n /* If we're disassembling an accumulator into a different type, we need\n-\t to emit a xxmfacc instruction now, since we cannot do it later. */\n- if (fncode == RS6000_BIF_DISASSEMBLE_ACC)\n+\t to emit a xxmfacc instruction now, since we cannot do it later. If we\n+\t have dense math registers, we don't need to do this. */\n+ if (fncode == RS6000_BIF_DISASSEMBLE_ACC && !TARGET_DENSE_MATH)\n \t{\n \t new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL];\n \t new_call = gimple_build_call (new_decl, 1, src);\ndiff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def\nindex dc67e287672..3e51848481f 100644\n--- a/gcc/config/rs6000/rs6000-cpus.def\n+++ b/gcc/config/rs6000/rs6000-cpus.def\n@@ -91,6 +91,7 @@\n will be fixed in potential future machines. */\n #define FUTURE_MASKS_SERVER\t(POWER11_MASKS_SERVER\t\t\t\\\n \t\t\t\t | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\t\\\n+\t\t\t\t | OPTION_MASK_DENSE_MATH\t\t\\\n \t\t\t\t | OPTION_MASK_FUTURE)\n \n /* Flags that need to be turned off if -mno-vsx. */\n@@ -124,6 +125,7 @@\n \t\t\t\t | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\t\\\n \t\t\t\t | OPTION_MASK_CMPB\t\t\t\\\n \t\t\t\t | OPTION_MASK_CRYPTO\t\t\t\\\n+\t\t\t\t | OPTION_MASK_DENSE_MATH\t\t\\\n \t\t\t\t | OPTION_MASK_DFP\t\t\t\\\n \t\t\t\t | OPTION_MASK_DLMZB\t\t\t\\\n \t\t\t\t | OPTION_MASK_EFFICIENT_UNALIGNED_VSX\t\\\ndiff --git a/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c b/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c\nnew file mode 100644\nindex 00000000000..deea87a0aa3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c\n@@ -0,0 +1,67 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_dense_math_ok } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+/* Test basic dense math support for MMA. */\n+\n+void\n+move_simple (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, 2 stxvp. */\n+ __vector_quad c = *a;\n+ *b = c;\n+}\n+\n+void\n+move_constraint_d (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, 2 stxvp. */\n+ __vector_quad c = *a;\n+ __asm__ (\" # %x0 (d constraint)\" : \"+d\" (c));\n+ *b = c;\n+}\n+\n+void\n+move_constraint_wD (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, dmxxinstdmr512, dmxxextfdmr512, 2 stxvp. */\n+ __vector_quad c = *a;\n+ __asm__ (\" # %A0 (wD constraint)\" : \"+wD\" (c));\n+ *b = c;\n+}\n+\n+void\n+clear_simple (__vector_quad *a)\n+{\n+ /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (a);\n+}\n+\n+void\n+clear_constraint_d (__vector_quad *a)\n+{\n+ __vector_quad z;\n+\n+ /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (&z);\n+ __asm__ (\" # %x0 (d constraint)\" : \"+d\" (z));\n+ *a = z;\n+}\n+\n+void\n+clear_constraint_wD (__vector_quad *a)\n+{\n+ __vector_quad z;\n+\n+ /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (&z);\n+ __asm__ (\" # %A0 (d constraint)\" : \"+wD\" (z));\n+ *a = z;\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mdmsetdmrz\\M} 3 } } */\n+/* { dg-final { scan-assembler-times {\\mdmxxextfdmr512\\M} 4 } } */\n+/* { dg-final { scan-assembler-times {\\mdmxxinstdmr512\\M} 1 } } */\n+/* { dg-final { scan-assembler-not {\\mxxmfacc\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mxxmtacc\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mxxsetaccz\\M} } } */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c b/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c\nnew file mode 100644\nindex 00000000000..091b71c94f7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c\n@@ -0,0 +1,67 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_dense_math_ok } */\n+/* { dg-options \"-mdejagnu-cpu=power10 -mno-dense-math -O2\" } */\n+\n+/* Test basic dense math support for MMA. */\n+\n+void\n+move_simple (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, xxmtacc, xxftacc 2 stxvp. */\n+ __vector_quad c = *a;\n+ *b = c;\n+}\n+\n+void\n+move_constraint_d (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, xxmtacc, xxftacc, 2 stxvp. */\n+ __vector_quad c = *a;\n+ __asm__ (\" # %x0 (d constraint)\" : \"+d\" (c));\n+ *b = c;\n+}\n+\n+void\n+move_constraint_wD (__vector_quad *a, __vector_quad *b)\n+{\n+ /* 2 lxvp, xxmtacc, xxftacc, 2 stxvp. */\n+ __vector_quad c = *a;\n+ __asm__ (\" # %A0 (wD constraint)\" : \"+wD\" (c));\n+ *b = c;\n+}\n+\n+void\n+clear_simple (__vector_quad *a)\n+{\n+ /* xxsetaccz, xxmfacc, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (a);\n+}\n+\n+void\n+clear_constraint_d (__vector_quad *a)\n+{\n+ __vector_quad z;\n+\n+ /* xxsetaccz, xxmfacc, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (&z);\n+ __asm__ (\" # %x0 (d constraint)\" : \"+d\" (z));\n+ *a = z;\n+}\n+\n+void\n+clear_constraint_wD (__vector_quad *a)\n+{\n+ __vector_quad z;\n+\n+ /* xxsetaccz, xxmfacc, 2 stxvp. */\n+ __builtin_mma_xxsetaccz (&z);\n+ __asm__ (\" # %A0 (d constraint)\" : \"+wD\" (z));\n+ *a = z;\n+}\n+\n+/* { dg-final { scan-assembler-not {\\mdmsetdmrz\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mdmxxextfdmr512\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mdmxxinstdmr512\\M} } } */\n+/* { dg-final { scan-assembler-times {\\mxxmfacc\\M} 6 } } */\n+/* { dg-final { scan-assembler-times {\\mxxmtacc\\M} 3 } } */\n+/* { dg-final { scan-assembler-times {\\mxxsetaccz\\M} 3 } } */\ndiff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp\nindex 64e7653e755..1b9e0bf8f49 100644\n--- a/gcc/testsuite/lib/target-supports.exp\n+++ b/gcc/testsuite/lib/target-supports.exp\n@@ -8029,6 +8029,25 @@ proc check_effective_target_power10_ok { } {\n }\n }\n \n+# Return 1 if this is a PowerPC target supporting -mcpu=future which enables\n+# the dense math operations.\n+proc check_effective_target_powerpc_dense_math_ok { } {\n+ if { ([istarget powerpc*-*-*]) } {\n+\treturn [check_no_compiler_messages powerpc_dense_math_ok object {\n+\t __vector_quad vq;\n+\t int main (void) {\n+\t\t/* Make sure we have dense math support. */\n+\t\t __vector_quad dmr;\n+\t\t __asm__ (\"dmsetaccz %A0\" : \"=wD\" (dmr));\n+\t\t vq = dmr;\n+\t\treturn 0;\n+\t }\n+\t} \"-mcpu=future\"]\n+ } else {\n+\treturn 0;\n+ }\n+}\n+\n # Return 1 if this is a PowerPC target supporting -mfloat128 via either\n # software emulation on power7/power8 systems or hardware support on power9.\n \n","prefixes":[]}