{"id":2225418,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225418/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/aebhzpi1c5BizfkE@cowardly-lion.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"","date":"2026-04-21T02:32:46","name":"GCC 17.0 PowerPC, Dense Math V6 [1/5]: Add wD constraint","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c86fabe49da93f1ab159c281062be5979aea1ae7","submitter":{"id":73991,"url":"http://patchwork.ozlabs.org/api/1.1/people/73991/?format=json","name":"Michael Meissner","email":"meissner@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/aebhzpi1c5BizfkE@cowardly-lion.the-meissners.org/mbox/","series":[{"id":500710,"url":"http://patchwork.ozlabs.org/api/1.1/series/500710/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=500710","date":"2026-04-21T02:32:46","name":"GCC 17.0 PowerPC, Dense Math V6 [1/5]: Add wD constraint","version":1,"mbox":"http://patchwork.ozlabs.org/series/500710/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225418/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225418/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=UvPSES9L;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"yXN296myT5Evr3h02eXH-tg0j40_FFmf","X-Proofpoint-ORIG-GUID":"yXN296myT5Evr3h02eXH-tg0j40_FFmf","X-Authority-Analysis":"v=2.4 cv=VP7tWdPX c=1 sm=1 tr=0 ts=69e6e1d6 cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=PNVkRuOr210gsube6MIA:9 a=CjuIK1q_8ugA:10","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIxMDAyMSBTYWx0ZWRfXyT0sajZyr9YV\n 2c7k6RT3RpaFTjHbx+R2SiC4kxE0SeLCW3tLNXDHS6bl22LenLtZLKqjtiNQzOioDquimooUBb7\n afg/irKddZEsTycwceoB9lO5wupHuq3FqFkLnVybbPqbkXZIGQEcRmppMVJ4Wodq77/t9nyIg2D\n 0e6Vol2sSwVGmv0JILeJq4U2AR7xO1fhXjQZTItotcovO/dOqzYhyGRKD7pZJM+BD3yZ6/mkp+i\n wNHTdCgeeT3LTDIHW0Uc5DSbgNCxMhgTJ9e5f8b50w5Zo8+PPOcDvmCxncXeYcJ8JKscgusZFm0\n ixUvAg93H/zYZXSlSmRpgA+wAIEbdxYctlv+vDZhv08DRmq5CvJBcGRZmiUeeWGPtvoW+pxnr0q\n m+30G1yfHC/PMA7+nfM1aMzDp83JU5c/MciIxvYSsyCLdfoHWXDrJzJujRyQchDd8+QejUG3GbZ\n cVc1oxX2UMEt26im3xg==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1015 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0\n spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210021","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Note, in the intro mail message, I said that this was V4 of the\npatches, but I missed I had submitted V5 on February 21st, 2026, so\nthis is now V6:\n\nThis is version 6 of the patches (which is the same as version 5).\nVersion 5 patches are at:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nThis patch adds a new constraint ('wD') that matches the accumulator registers\nused by the MMA instructions. Possible future PowerPC machines are thinking\nabout having a new set of 8 dense math accumulators that will be 1,024 bits in\nsize. The 'wD' constaint was chosen because the VSX constraints start with 'w'.\nThe 'wd' constraint was already used, so I chose 'wD' to be similar.\n\nTo change code to possibly use dense math registers, the 'd' constraint should\nbe changed to 'wD', and the predicate 'fpr_reg_operand' should be changed to\n'accumulator_operand'.\n\nOn current power10/power11 systems, the accumulators overlap with the 32\ntraditional FPR registers (i.e. VSX vector registers 0..31). Each accumulator\nuses 4 adjacent FPR/VSX registers for a 512 bit logical register.\n\nPossible future PowerPC machines would have these 8 accumulator registers be\nseparate registers, called dense math registers. It is anticipated that when in\ndense math register mode, the MMA instructions would use the accumulators\ninstead of the adjacent VSX registers. I.e. in power10/power11 mode,\naccumulator 1 will overlap with vector registers 4-7, but in dense math register\nmode, accumulator 1 will be a separate register.\n\nCode compiled for power10/power11 systems will continue to work on the potential\nfuture machine with dense math register support but the compiler will have fewer\nvector registers available for allocation because it believe the accumulators\nare using vector registers. For example, the file mma-double-test.c in the\ngcc.target/powerpc testsuite directory has 8 more register spills to/from the\nstack for power10/power11 code then when compiled with dense math register\nsupport.\n\nIn this patch, I have removed using the wD constriant in mma.md. A later patch\nwill change mma.md to using wA instead of a d constraint.\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\n2026-04-20 Michael Meissner \n\n\t* config/rs6000/constraints.md (wD): New constraint.\n\t* config/rs6000/predicates.md (accumulator_operand): New predicate.\n\t* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Print the register\n\tclass for the 'wD' constraint.\n\t(rs6000_init_hard_regno_mode_ok): Set up the 'wD' register constraint\n\tclass.\n\t* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add element for\n\tthe 'wD' constraint.\n\t* doc/md.texi (PowerPC constraints): Document the 'wD' constraint.\n\n---\n gcc/config/rs6000/constraints.md | 3 +++\n gcc/config/rs6000/predicates.md | 18 ++++++++++++++++++\n gcc/config/rs6000/rs6000.cc | 7 ++++++-\n gcc/config/rs6000/rs6000.h | 1 +\n gcc/doc/md.texi | 5 +++++\n 5 files changed, 33 insertions(+), 1 deletion(-)","diff":"diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md\nindex d0ed47faab8..0d1cde5bd4d 100644\n--- a/gcc/config/rs6000/constraints.md\n+++ b/gcc/config/rs6000/constraints.md\n@@ -107,6 +107,9 @@ (define_constraint \"wB\"\n (match_test \"TARGET_P8_VECTOR\")\n (match_operand 0 \"s5bit_cint_operand\")))\n \n+(define_register_constraint \"wD\" \"rs6000_constraints[RS6000_CONSTRAINT_wD]\"\n+ \"Accumulator register.\")\n+\n (define_constraint \"wE\"\n \"@internal Vector constant that can be loaded with the XXSPLTIB instruction.\"\n (match_test \"xxspltib_constant_nosplit (op, mode)\"))\ndiff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md\nindex 54dbc8bcc95..682fd2dc6e8 100644\n--- a/gcc/config/rs6000/predicates.md\n+++ b/gcc/config/rs6000/predicates.md\n@@ -186,6 +186,24 @@ (define_predicate \"vlogical_operand\"\n return VLOGICAL_REGNO_P (REGNO (op));\n })\n \n+;; Return 1 if op is an accumulator. On power10 systems, the accumulators\n+;; overlap with the FPRs.\n+(define_predicate \"accumulator_operand\"\n+ (match_operand 0 \"register_operand\")\n+{\n+ if (SUBREG_P (op))\n+ op = SUBREG_REG (op);\n+\n+ if (!REG_P (op))\n+ return 0;\n+\n+ if (!HARD_REGISTER_P (op))\n+ return 1;\n+\n+ int r = REGNO (op);\n+ return FP_REGNO_P (r) && (r & 3) == 0;\n+})\n+\n ;; Return 1 if op is the carry register.\n (define_predicate \"ca_operand\"\n (match_operand 0 \"register_operand\")\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex 4999cb6f54e..63723396558 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -2328,6 +2328,7 @@ rs6000_debug_reg_global (void)\n \t \"wr reg_class = %s\\n\"\n \t \"wx reg_class = %s\\n\"\n \t \"wA reg_class = %s\\n\"\n+\t \"wD reg_class = %s\\n\"\n \t \"\\n\",\n \t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],\n \t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],\n@@ -2335,7 +2336,8 @@ rs6000_debug_reg_global (void)\n \t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],\n \t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],\n \t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],\n-\t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);\n+\t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],\n+\t reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);\n \n nl = \"\\n\";\n for (m = 0; m < NUM_MACHINE_MODES; ++m)\n@@ -2992,6 +2994,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n if (TARGET_DIRECT_MOVE_128)\n rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;\n \n+ if (TARGET_MMA)\n+ rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;\n+\n /* Set up the reload helper and direct move functions. */\n if (TARGET_VSX || TARGET_ALTIVEC)\n {\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex 2d3016db513..04709f0dcd6 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -1183,6 +1183,7 @@ enum r6000_reg_class_enum {\n RS6000_CONSTRAINT_wr,\t\t/* GPR register if 64-bit */\n RS6000_CONSTRAINT_wx,\t\t/* FPR register for STFIWX */\n RS6000_CONSTRAINT_wA,\t\t/* BASE_REGS if 64-bit. */\n+ RS6000_CONSTRAINT_wD,\t\t/* Accumulator regs if MMA/Dense Math. */\n RS6000_CONSTRAINT_MAX\n };\n \ndiff --git a/gcc/doc/md.texi b/gcc/doc/md.texi\nindex 6af646e3e01..d70e7beb52e 100644\n--- a/gcc/doc/md.texi\n+++ b/gcc/doc/md.texi\n@@ -3415,6 +3415,11 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.\n @item wA\n Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.\n \n+@item wD\n+Accumulator register if @option{-mma} is used; otherwise,\n+@code{NO_REGS}. For @option{-mcpu=power10} the accumulator registers\n+overlap with VSX vector registers 0..31.\n+\n @item wB\n Signed 5-bit constant integer that can be loaded into an Altivec register.\n \n","prefixes":[]}