{"id":2225224,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225224/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260420163500.4138411-1-gurumoorthy.santhakumar@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260420163500.4138411-1-gurumoorthy.santhakumar@oss.qualcomm.com>","date":"2026-04-20T16:35:00","name":"[v1] serial: msm-geni: configure RX watermark register","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"66762573e59900d063c4db2abcacb7208f49134f","submitter":{"id":93144,"url":"http://patchwork.ozlabs.org/api/1.1/people/93144/?format=json","name":"Gurumoorthy Santhakumar","email":"gurumoorthy.santhakumar@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.1/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260420163500.4138411-1-gurumoorthy.santhakumar@oss.qualcomm.com/mbox/","series":[{"id":500634,"url":"http://patchwork.ozlabs.org/api/1.1/series/500634/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500634","date":"2026-04-20T16:35:00","name":"[v1] serial: msm-geni: configure RX watermark register","version":1,"mbox":"http://patchwork.ozlabs.org/series/500634/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225224/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225224/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Z26rdLn3;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=CoTcccj3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Z26rdLn3\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"CoTcccj3\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=gurumoorthy.santhakumar@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzrgs2T9Vz1yD4\n\tfor ; Tue, 21 Apr 2026 02:35:21 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id AF0BF842B7;\n\tMon, 20 Apr 2026 18:35:18 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id E33AD842BF; Mon, 20 Apr 2026 18:35:17 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id BE60784258\n for ; Mon, 20 Apr 2026 18:35:12 +0200 (CEST)","from pps.filterd (m0279870.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63KCxJin3455879\n for ; Mon, 20 Apr 2026 16:35:11 GMT","from mail-pl1-f200.google.com (mail-pl1-f200.google.com\n [209.85.214.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dnfvjt6xp-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 20 Apr 2026 16:35:11 +0000 (GMT)","by mail-pl1-f200.google.com with SMTP id\n d9443c01a7336-2b2e6ee9444so35492405ad.1\n for ; Mon, 20 Apr 2026 09:35:11 -0700 (PDT)","from hu-gsanthak-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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gurumoorthy.santhakumar@oss.qualcomm.com,\n u-boot-qcom@groups.io, u-boot@lists.denx.de","Subject":"[PATCH v1] serial: msm-geni: configure RX watermark register","Date":"Mon, 20 Apr 2026 22:05:00 +0530","Message-Id":"\n <20260420163500.4138411-1-gurumoorthy.santhakumar@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"J3wsziB5zB3fs-Q_ASphUzxE5qKCFJIE","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIwMDE1OSBTYWx0ZWRfX8zphEsPmGn6j\n 0lLSP+Cal372zUp3jFltJmRmvUqYFU4snSKvtvYaXUOzggu0nyo0loFBRTvT8OeF9b8Ia9udIPa\n DTJvs4ZAiFgHT781B+OpYnpgf4KXWcULwDuK8Fls7K4TRvVIqSap4+A28sYTypaKvNgCnMKbp1O\n wEdPor+9mdXILfyX8QES9ILQagPnIMDKtCbvmWec/ZgTOaV+YTRNFT02t+bjoxlCiHTvB5O2sly\n Ca6e9DzJ4zdV6+ZPHLoqzVObW7MtH9fyzACfn1zW4Kt4pCMz59zqQ6/G7W4IMRwB8sGeBzJiFHu\n wRpRognV4gAHD3BkB1EbbSUAGDKu9VXRv6yylaFZ409eqCaFbjnTFgYsQnANxpzbSCzDu3iVN8v\n gdFQU5Dwe+v6pVoG+p82tB5m+9hUxEKXkL9zF60kfY1c1QHYYE2hKo8crj6W8c8XYSYhW21rOIU\n iayi5lpi7v4lDxigBvw==","X-Authority-Analysis":"v=2.4 cv=XNMAjwhE c=1 sm=1 tr=0 ts=69e655bf cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8\n a=ag1SF4gXAAAA:8 a=EUspDBNiAAAA:8 a=JQEU1KsGukfSeQCV5iwA:9\n a=uG9DUKGECoFWVXl0Dc02:22 a=Yupwre4RP9_Eg_Bd0iYG:22","X-Proofpoint-GUID":"J3wsziB5zB3fs-Q_ASphUzxE5qKCFJIE","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_03,2026-04-20_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015\n phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200159","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX\nsetup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(),\nmsm_geni_serial_setup_rx() and _debug_uart_init() to align with the\nLinux kernel driver behaviour.\n\nWithout this, the RX FIFO watermark interrupt threshold is left at\nits hardware reset value, which may differ from the expected value\nand can cause RX data loss or missed watermark interrupts.\n\nLink: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/\nSigned-off-by: Gurumoorthy Santhakumar \n---\n drivers/serial/serial_msm_geni.c | 4 ++++\n 1 file changed, 4 insertions(+)","diff":"diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c\nindex 3dca581f68f..ae4015e0fdc 100644\n--- a/drivers/serial/serial_msm_geni.c\n+++ b/drivers/serial/serial_msm_geni.c\n@@ -55,6 +55,7 @@\n #define SE_UART_RX_PARITY_CFG\t0x2a8\n \n #define DEF_TX_WM\t2\n+#define DEF_RX_WM\t2\n /* GENI_FORCE_DEFAULT_REG fields */\n \n #define UART_START_READ\t0x1\n@@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev)\n \n \tgeni_se_setup_s_cmd(priv->base, UART_START_READ, 0);\n \n+\twritel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);\n \tsetbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);\n \tsetbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);\n }\n@@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev)\n \n \tgeni_se_setup_s_cmd(priv->base, UART_START_READ, 0);\n \n+\twritel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);\n \tsetbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);\n \tsetbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);\n }\n@@ -616,6 +619,7 @@ static inline void _debug_uart_init(void)\n \tphys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);\n \n \tgeni_serial_init(&init_dev);\n+\twritel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG);\n \tgeni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);\n \tqcom_geni_serial_start_tx(base);\n }\n","prefixes":["v1"]}