{"id":2225104,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225104/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-7-biju.das.jz@bp.renesas.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104332.153640-7-biju.das.jz@bp.renesas.com>","date":"2026-04-20T10:43:23","name":"[v5,6/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0f6cfad189db4dfdb971be7d8747e34f069b068e","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-7-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":500593,"url":"http://patchwork.ozlabs.org/api/1.1/series/500593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593","date":"2026-04-20T10:43:17","name":"Add Renesas RZ/G3E GPT support","version":5,"mbox":"http://patchwork.ozlabs.org/series/500593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225104/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225104/checks/","tags":{},"headers":{"Return-Path":"\n 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","X-Google-Original-From":"Biju ","To":"=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= ","Cc":"Biju Das ,\n\tlinux-pwm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tGeert Uytterhoeven ,\n\tPrabhakar Mahadev Lad ,\n\tBiju Das ,\n\tlinux-renesas-soc@vger.kernel.org,\n\tTommaso Merciai ","Subject":"[PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct\n rzg2l_gpt_info","Date":"Mon, 20 Apr 2026 11:43:23 +0100","Message-ID":"<20260420104332.153640-7-biju.das.jz@bp.renesas.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260420104332.153640-1-biju.das.jz@bp.renesas.com>","References":"<20260420104332.153640-1-biju.das.jz@bp.renesas.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"From: Biju Das \n\nRZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.\nAdd prescale_mult variable to struct rzg2l_gpt_info for handling this\ndifference.\n\nReviewed-by: Tommaso Merciai \nSigned-off-by: Biju Das \n---\nv4->v5:\n * No change.\nv3->v4:\n * Updated commit header and description\n * Renamed prescale_pow_of_two_mult_factor->prescale_mult\nv2->v3:\n * No change.\nv1->v2:\n * Collected tag.\n---\n drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++------\n 1 file changed, 13 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\nindex af594c1ce536..4324ffc8629d 100644\n--- a/drivers/pwm/pwm-rzg2l-gpt.c\n+++ b/drivers/pwm/pwm-rzg2l-gpt.c\n@@ -92,6 +92,7 @@\n \n struct rzg2l_gpt_info {\n \tu32 gtcr_tpcs;\n+\tu8 prescale_mult;\n };\n \n struct rzg2l_gpt_chip {\n@@ -234,6 +235,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,\n static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n \t\t\t\t\t u32 val, u8 prescale)\n {\n+\tconst struct rzg2l_gpt_info *info = rzg2l_gpt->info;\n \tu64 tmp;\n \n \t/*\n@@ -243,15 +245,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n \t * < 2^32 * 2^10 * 2^20\n \t * = 2^62\n \t */\n-\ttmp = (u64)val << (2 * prescale);\n+\ttmp = (u64)val << (info->prescale_mult * prescale);\n \ttmp *= USEC_PER_SEC;\n \n \treturn DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);\n }\n \n-static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)\n+static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,\n+\t\t\t\t\tu64 period_or_duty_cycle, u8 prescale)\n {\n-\treturn min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),\n+\treturn min_t(u64,\n+\t\t DIV_ROUND_DOWN_ULL(period_or_duty_cycle,\n+\t\t\t\t\t1 << (info->prescale_mult * prescale)),\n \t\t U32_MAX);\n }\n \n@@ -262,6 +267,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n \n {\n \tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n+\tconst struct rzg2l_gpt_info *info = rzg2l_gpt->info;\n \tstruct rzg2l_gpt_waveform *wfhw = _wfhw;\n \tbool is_small_second_period = false;\n \tu8 ch = RZG2L_GET_CH(pwm->hwpwm);\n@@ -299,8 +305,8 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n \t\t}\n \t}\n \n-\twfhw->prescale = rzg2l_gpt_calculate_prescale(period_ticks);\n-\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);\n+\twfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);\n+\tpv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);\n \twfhw->gtpr = pv;\n \twfhw->gtccr = 0;\n \tif (is_small_second_period)\n@@ -309,7 +315,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n \tduty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n \tif (duty_ticks > RZG2L_MAX_TICKS)\n \t\tduty_ticks = RZG2L_MAX_TICKS;\n-\tdc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);\n+\tdc = rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale);\n \twfhw->gtccr = dc;\n \n \t/*\n@@ -582,6 +588,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \n static const struct rzg2l_gpt_info rzg2l_data = {\n \t.gtcr_tpcs = RZG2L_GTCR_TPCS,\n+\t.prescale_mult = 2,\n };\n \n static const struct of_device_id rzg2l_gpt_of_table[] = {\n","prefixes":["v5","6/9"]}