{"id":2225103,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225103/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-29-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104248.86702-29-mohamed@unpredictable.fr>","date":"2026-04-20T10:42:38","name":"[v2,28/38] whpx: i386: CPU features support for Windows 10","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"32450f5ec66923929287a1eb2f020768cebf59d6","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-29-mohamed@unpredictable.fr/mbox/","series":[{"id":500592,"url":"http://patchwork.ozlabs.org/api/1.1/series/500592/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500592","date":"2026-04-20T10:42:10","name":"WHPX x86 updates for QEMU 11.1","version":2,"mbox":"http://patchwork.ozlabs.org/series/500592/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225103/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225103/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=WjxOkqnT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzj0F3rzMz1yCv\n\tfor ; Mon, 20 Apr 2026 20:49:01 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEm6t-0008Dv-PI; Mon, 20 Apr 2026 06:44:11 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEm6s-0008DT-Dz\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:44:10 -0400","from p-west3-cluster4-host7-snip4-10.eps.apple.com ([57.103.74.141]\n helo=outbound.ms.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEm6p-0000jn-Q6\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:44:10 -0400","from outbound.ms.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPS id\n E81E01800097; Mon, 20 Apr 2026 10:44:03 +0000 (UTC)","from localhost.localdomain (unknown [17.57.154.37])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPSA id\n 117B918000BF; Mon, 20 Apr 2026 10:44:00 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776681846; x=1779273846;\n bh=FjknWeXX453ZkdimgET5qsOfRjRd950mgDj8NKv+vI4=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=WjxOkqnT6BYcEYghIml7QL5elXP1nICipH6tp0q11gTIZ5N2uiUU/1iip5tlAVK6nkK9yQaZ0r0aeDNYbadzeTki5PGUQRz0umBgz9DxQBMGirqKymceiQNLoHVgdu9TBD2gLIS2bNob5rO6gSu+oAqCyHMLPKxbFZAYPrxH7Ztln3wQFHUH36m0wGmDdLLolhypKTbjSM3on9y2axrbEw2WSGbhmh2DuhnHQxpRkvX4+v+qtIDLh86b+bSIANg4i9wMtF6F8vjhsd9EzRnaB/SulX01Ak1MG0p8+TwyhjLUDGtyNQTZiKpIeXUCQOK7Bg3CYesjqTeCS9ZGAs2SUw==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org, Mohamed Mediouni ,\n Paolo Bonzini ,\n Phil Dennis-Jordan ,\n Roman Bolshakov ,\n Pierrick Bouvier ,\n Pedro Barbuda , Wei Liu ,\n \"Michael S. Tsirkin\" ,\n Peter Maydell , Zhao Liu ","Subject":"[PATCH v2 28/38] whpx: i386: CPU features support for Windows 10","Date":"Mon, 20 Apr 2026 12:42:38 +0200","Message-ID":"<20260420104248.86702-29-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260420104248.86702-1-mohamed@unpredictable.fr>","References":"<20260420104248.86702-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Authority-Info-Out":"v=2.4 cv=MK9tWcZl c=1 sm=1 tr=0 ts=69e60375\n cx=c_apl:c_pps:t_out a=qkKslKyYc0ctBTeLUVfTFg==:117 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=mDV3o1hIAAAA:8 a=_S2v2Z1saO19s7bx6VoA:9","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIwMDEwNCBTYWx0ZWRfXwrsj3Z7EXcXk\n I9fsIzwlp0yO5cN5k2aYwiF19k+LSRfIwaxClZrkiSmwvX64gBiro/9Twh5UODQCLa9Sv10MzZH\n HU1H6Sg850six0E/KI+s288qCVw1oYmY/hCKLYfbREGK8DcqSvBCt9menXrXIiiT7reIRg86NFI\n U7DakHPEdvfw9puku6/xojJHoHfgtzWXF7uVXXeN06qk9yFWZXI54YBVJryYg6R9ttjvCov2ADt\n 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DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Mohamed Mediouni \n---\n target/i386/cpu.c | 18 +--\n target/i386/whpx/meson.build | 1 +\n target/i386/whpx/whpx-all.c | 38 ++++++-\n target/i386/whpx/whpx-cpu-legacy.c | 171 +++++++++++++++++++++++++++++\n target/i386/whpx/whpx-i386.h | 7 ++\n 5 files changed, 215 insertions(+), 20 deletions(-)\n create mode 100644 target/i386/whpx/whpx-cpu-legacy.c","diff":"diff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex b18e40666e..8f090782bd 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -8092,9 +8092,6 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w)\n } else if (whpx_enabled()) {\n if (wi->type != CPUID_FEATURE_WORD) {\n return 0;\n- }\n- if (whpx_is_legacy_os()) {\n- r = wi->tcg_features;\n } else {\n r = whpx_get_supported_cpuid(wi->cpuid.eax,\n wi->cpuid.ecx,\n@@ -8182,17 +8179,10 @@ static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,\n *ecx = hvf_get_supported_cpuid(func, index, R_ECX);\n *edx = hvf_get_supported_cpuid(func, index, R_EDX);\n } else if (whpx_enabled()) {\n- if (whpx_is_legacy_os()) {\n- *eax = 0;\n- *ebx = 0;\n- *ecx = 0;\n- *edx = 0;\n- } else {\n- *eax = whpx_get_supported_cpuid(func, index, R_EAX);\n- *ebx = whpx_get_supported_cpuid(func, index, R_EBX);\n- *ecx = whpx_get_supported_cpuid(func, index, R_ECX);\n- *edx = whpx_get_supported_cpuid(func, index, R_EDX);\n- }\n+ *eax = whpx_get_supported_cpuid(func, index, R_EAX);\n+ *ebx = whpx_get_supported_cpuid(func, index, R_EBX);\n+ *ecx = whpx_get_supported_cpuid(func, index, R_ECX);\n+ *edx = whpx_get_supported_cpuid(func, index, R_EDX);\n } else {\n *eax = 0;\n *ebx = 0;\ndiff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build\nindex c3aaaff9fd..1c6a4ce377 100644\n--- a/target/i386/whpx/meson.build\n+++ b/target/i386/whpx/meson.build\n@@ -1,4 +1,5 @@\n i386_system_ss.add(when: 'CONFIG_WHPX', if_true: files(\n 'whpx-all.c',\n 'whpx-apic.c',\n+ 'whpx-cpu-legacy.c'\n ))\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 02235d5391..045dbdfdc8 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -270,11 +270,30 @@ typedef enum WhpxStepMode {\n static uint32_t max_vcpu_index;\n static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap;\n \n-static bool whpx_has_xsave(void)\n+bool whpx_has_xsave(void)\n {\n return whpx_xsave_cap.XsaveSupport;\n }\n \n+bool whpx_has_xsaves(void)\n+{\n+ return whpx_xsave_cap.XsaveSupervisorSupport;\n+}\n+\n+static bool whpx_rdtsc_cap;\n+\n+bool whpx_has_rdtscp(void)\n+{\n+ return whpx_rdtsc_cap;\n+}\n+\n+static bool whpx_invpcid_cap;\n+\n+bool whpx_has_invpcid(void)\n+{\n+ return whpx_invpcid_cap;\n+}\n+\n static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v86,\n int r86)\n {\n@@ -1057,6 +1076,11 @@ uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg)\n bool temp_cpu = true;\n HRESULT hr;\n \n+ /* Legacy OSes don't have WHvGetVirtualProcessorCpuidOutput */\n+ if (whpx_is_legacy_os()) {\n+ return whpx_get_supported_cpuid_legacy(func, idx, reg);\n+ }\n+\n hr = whp_dispatch.WHvCreateVirtualProcessor(\n whpx_global.partition, cpu_index, 0);\n \n@@ -2147,7 +2171,7 @@ int whpx_vcpu_run(CPUState *cpu)\n * just pass through what the hypervisor\n * provides without any QEMU filtering.\n */\n- if (whpx_is_legacy_os() || xcc->max_features) {\n+ if (xcc->max_features) {\n reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;\n reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;\n reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;\n@@ -2507,11 +2531,11 @@ void whpx_cpu_instance_init(CPUState *cs)\n host_cpu_instance_init(cpu);\n x86_cpu_apply_props(cpu, whpx_default_props);\n \n- if (!whpx_is_legacy_os() && xcc->max_features) {\n+ if (xcc->max_features) {\n whpx_cpu_max_instance_init(cpu);\n }\n \n- if (!whpx_is_legacy_os()) {\n+ if (whpx_has_xsave()) {\n whpx_cpu_xsave_init();\n }\n }\n@@ -2536,7 +2560,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n 0x40000000, 0x40000001, 0x40000010, 0x80000000, 0x80000001,\n 0x80000002, 0x80000003, 0x80000004, 0x80000007, 0x80000008,\n 0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001};\n- UINT32 cpuidExitList_legacy_os[] = {1, 0x40000000, 0x40000001, 0x40000010};\n \n X86MachineState *x86ms = X86_MACHINE(ms);\n bool pic_enabled = false;\n@@ -2700,6 +2723,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n goto error;\n }\n \n+ whpx_rdtsc_cap = processor_features.Bank0.RdtscpSupport;\n+ whpx_invpcid_cap = processor_features.Bank0.InvpcidSupport;\n+\n if (whpx_irqchip_in_kernel() && processor_features.Bank1.NestedVirtSupport) {\n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.NestedVirtualization = 1;\n@@ -2808,7 +2834,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\n WHvPartitionPropertyCodeCpuidExitList,\n- !whpx_is_legacy_os() ? cpuidExitList : cpuidExitList_legacy_os,\n+ cpuidExitList,\n RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));\n \n if (FAILED(hr)) {\ndiff --git a/target/i386/whpx/whpx-cpu-legacy.c b/target/i386/whpx/whpx-cpu-legacy.c\nnew file mode 100644\nindex 0000000000..477429b460\n--- /dev/null\n+++ b/target/i386/whpx/whpx-cpu-legacy.c\n@@ -0,0 +1,171 @@\n+/*\n+ * i386 CPUID helper functions\n+ *\n+ * Copyright (c) 2003 Fabrice Bellard\n+ * Copyright (c) 2017 Google Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU Lesser General Public\n+ * License as published by the Free Software Foundation; either\n+ * version 2.1 of the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public\n+ * License along with this program; if not, see .\n+ *\n+ * cpuid\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/cpuid.h\"\n+#include \"host/cpuinfo.h\"\n+#include \"cpu.h\"\n+#include \"emulate/x86.h\"\n+#include \"whpx-i386.h\"\n+\n+static bool cached_xcr0;\n+static uint64_t supported_xcr0;\n+\n+static void cache_host_xcr0(void)\n+{\n+ if (cached_xcr0) {\n+ return;\n+ }\n+\n+ if (whpx_has_xsave()) {\n+ uint64_t host_xcr0 = xgetbv_low(0);\n+\n+ /* Only show xcr0 bits corresponding to usable features. */\n+ supported_xcr0 = host_xcr0 & (XSTATE_FP_MASK |\n+ XSTATE_SSE_MASK | XSTATE_YMM_MASK |\n+ XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK |\n+ XSTATE_Hi16_ZMM_MASK);\n+ if ((supported_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK)) !=\n+ (XSTATE_FP_MASK | XSTATE_SSE_MASK)) {\n+ supported_xcr0 = 0;\n+ }\n+ }\n+\n+ cached_xcr0 = true;\n+}\n+\n+uint32_t whpx_get_supported_cpuid_legacy(uint32_t func, uint32_t idx,\n+ int reg)\n+{\n+ uint32_t eax, ebx, ecx, edx;\n+\n+ cache_host_xcr0();\n+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);\n+\n+ switch (func) {\n+ case 0:\n+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;\n+ break;\n+ case 1:\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |\n+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_HT;\n+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |\n+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |\n+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |\n+ CPUID_EXT_POPCNT | CPUID_EXT_AES |\n+ (supported_xcr0 ? CPUID_EXT_XSAVE : 0) |\n+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;\n+ ecx |= CPUID_EXT_HYPERVISOR;\n+ ecx |= CPUID_EXT_X2APIC;\n+ edx |= CPUID_HT;\n+ break;\n+ case 6:\n+ eax = CPUID_6_EAX_ARAT;\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ break;\n+ case 7:\n+ if (idx == 0) {\n+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |\n+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |\n+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |\n+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |\n+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |\n+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |\n+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |\n+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |\n+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |\n+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |\n+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |\n+ CPUID_7_0_EBX_INVPCID;\n+\n+ if (!whpx_has_invpcid()) {\n+ ebx &= ~CPUID_7_0_EBX_INVPCID;\n+ }\n+\n+ ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ |\n+ CPUID_7_0_ECX_RDPID;\n+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;\n+ } else {\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ }\n+ eax = 0;\n+ break;\n+ case 0xD:\n+ if (!supported_xcr0 || idx >= 63 ||\n+ (idx > 1 && !(supported_xcr0 & (UINT64_C(1) << idx)))) {\n+ eax = ebx = ecx = edx = 0;\n+ break;\n+ }\n+\n+ if (idx == 0) {\n+ eax = supported_xcr0;\n+ } else if (idx == 1) {\n+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;\n+ if (!whpx_has_xsaves()) {\n+ eax &= ~CPUID_XSAVE_XSAVES;\n+ }\n+ }\n+ break;\n+ case 0x80000001:\n+ /* LM only if HVF in 64-bit mode */\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |\n+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |\n+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;\n+ if (!(whpx_has_rdtscp())) {\n+ edx &= ~CPUID_EXT2_RDTSCP;\n+ }\n+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |\n+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |\n+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |\n+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;\n+ break;\n+ case 0x80000007:\n+ edx &= CPUID_APM_INVTSC;\n+ eax = ebx = ecx = 0;\n+ break;\n+ default:\n+ return 0;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\ndiff --git a/target/i386/whpx/whpx-i386.h b/target/i386/whpx/whpx-i386.h\nindex 6db9a75d39..9dc6837574 100644\n--- a/target/i386/whpx/whpx-i386.h\n+++ b/target/i386/whpx/whpx-i386.h\n@@ -2,3 +2,10 @@\n \n uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg);\n bool whpx_is_legacy_os(void);\n+\n+uint32_t whpx_get_supported_cpuid_legacy(uint32_t func, uint32_t idx,\n+ int reg);\n+bool whpx_has_xsave(void);\n+bool whpx_has_xsaves(void);\n+bool whpx_has_rdtscp(void);\n+bool whpx_has_invpcid(void);\n","prefixes":["v2","28/38"]}