{"id":2225090,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225090/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-2-biju.das.jz@bp.renesas.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104332.153640-2-biju.das.jz@bp.renesas.com>","date":"2026-04-20T10:43:18","name":"[v5,1/9] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d45638942494a79b610d489d8043720dd0542a94","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-2-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":500593,"url":"http://patchwork.ozlabs.org/api/1.1/series/500593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593","date":"2026-04-20T10:43:17","name":"Add Renesas RZ/G3E GPT support","version":5,"mbox":"http://patchwork.ozlabs.org/series/500593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225090/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225090/checks/","tags":{},"headers":{"Return-Path":"\n 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<biju.das.au@gmail.com>","X-Google-Original-From":"Biju <biju.das.jz@bp.renesas.com>","To":"=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Magnus Damm <magnus.damm@gmail.com>","Cc":"Biju Das <biju.das.jz@bp.renesas.com>,\n\tlinux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tPrabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tBiju Das <biju.das.au@gmail.com>","Subject":"[PATCH v5 1/9] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs\n property","Date":"Mon, 20 Apr 2026 11:43:18 +0100","Message-ID":"<20260420104332.153640-2-biju.das.jz@bp.renesas.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260420104332.153640-1-biju.das.jz@bp.renesas.com>","References":"<20260420104332.153640-1-biju.das.jz@bp.renesas.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"<linux-pwm.vger.kernel.org>","List-Subscribe":"<mailto:linux-pwm+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-pwm+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"From: Biju Das <biju.das.jz@bp.renesas.com>\n\nRZ/G2L GPT IP supports output pin disable function by dead time\nerror and detecting short-circuits between output pins.\n\nAdd documentation for the optional property renesas,poegs to\nlink a pair of GPT IOs with POEG.\n\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv5:\n * No change\nv24 from [1]:\n[1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.renesas.com/\n---\n .../bindings/pwm/renesas,rzg2l-gpt.yaml       | 23 +++++++++++++++++++\n 1 file changed, 23 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml\nindex 13b807765a30..98bcde755fb9 100644\n--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml\n+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml\n@@ -245,6 +245,28 @@ properties:\n   resets:\n     maxItems: 1\n \n+  renesas,poegs:\n+    minItems: 1\n+    maxItems: 8\n+    $ref: /schemas/types.yaml#/definitions/phandle-array\n+    items:\n+      items:\n+        - description: phandle to POEG instance that serves the output disable\n+        - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]\n+          description: |\n+            An index identifying pair of GPT channels.\n+              <0> : GPT channels 0 and 1\n+              <1> : GPT channels 2 and 3\n+              <2> : GPT channels 4 and 5\n+              <3> : GPT channels 6 and 7\n+              <4> : GPT channels 8 and 9\n+              <5> : GPT channels 10 and 11\n+              <6> : GPT channels 12 and 13\n+              <7> : GPT channels 14 and 15\n+    description:\n+      A list of phandle and channel index pair tuples to the POEGs that handle the\n+      output disable for the GPT channels.\n+\n required:\n   - compatible\n   - reg\n@@ -375,4 +397,5 @@ examples:\n         power-domains = <&cpg>;\n         resets = <&cpg R9A07G044_GPT_RST_C>;\n         #pwm-cells = <3>;\n+        renesas,poegs = <&poeggd 4>;\n     };\n","prefixes":["v5","1/9"]}