{"id":2225081,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225081/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-9-biju.das.jz@bp.renesas.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104332.153640-9-biju.das.jz@bp.renesas.com>","date":"2026-04-20T10:43:25","name":"[v5,8/9] dt-bindings: pwm: Document RZ/G3E GPT support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6f898badc6487268160d8df77f51040607356ee0","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-9-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":500593,"url":"http://patchwork.ozlabs.org/api/1.1/series/500593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593","date":"2026-04-20T10:43:17","name":"Add Renesas RZ/G3E GPT support","version":5,"mbox":"http://patchwork.ozlabs.org/series/500593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225081/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225081/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=NT5IKr4s;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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The hardware supports simultaneous control of\nall channels. PWM waveforms can be generated by controlling the\nup-counter, downcounter, or up- and down-counter.\n\nReviewed-by: Rob Herring (Arm) \nSigned-off-by: Biju Das \n---\nv4->v5:\n * No change.\nv3->v4:\n * No change.\nv2->v3:\n * Added Rb tag from Rob.\nv1->v2:\n * Created separate document for RZ/G3E GPT.\n * Updated commit header and description.\n---\n .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++\n 1 file changed, 323 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml","diff":"diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml\nnew file mode 100644\nindex 000000000000..cb4ffab5f47f\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml\n@@ -0,0 +1,323 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Renesas RZ/G3E General PWM Timer (GPT)\n+\n+maintainers:\n+ - Biju Das \n+\n+description: |\n+ RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit\n+ timer. It supports the following functions\n+ * 32 bits x 16 channels.\n+ * Up-counting or down-counting (saw waves) or up/down-counting\n+ (triangle waves) for each counter.\n+ * Clock sources independently selectable for each channel.\n+ * Four I/O pins per channel.\n+ * Two output compare/input capture registers per channel.\n+ * For the two output compare/input capture registers of each channel,\n+ four registers are provided as buffer registers and are capable of\n+ operating as comparison registers when buffering is not in use.\n+ * In output compare operation, buffer switching can be at crests or\n+ troughs, enabling the generation of laterally asymmetric PWM waveforms.\n+ * Registers for setting up frame cycles in each channel (with capability\n+ for generating interrupts at overflow or underflow)\n+ * Generation of dead times in PWM operation.\n+ * Synchronous starting, stopping and clearing counters for arbitrary\n+ channels.\n+ * Count start, count stop, count clear, up-count, down-count, or input\n+ capture operation in response to a maximum of 8 ELC events.\n+ * Count start, count stop, count clear, up-count, down-count, or input\n+ capture operation in response to the status of two input pins.\n+ * Starting, clearing, stopping and up/down counters in response to a\n+ maximum of four external triggers.\n+ * Output pin disable function by detected short-circuits between output\n+ pins.\n+ * A/D converter start triggers can be generated.\n+ * Compare match A to F event and overflow/underflow event can be output\n+ to the ELC.\n+ * Enables the noise filter for input capture.\n+ * Logical operation between the channel output.\n+\n+properties:\n+ compatible:\n+ items:\n+ - const: renesas,r9a09g047-gpt # RZ/G3E\n+\n+ reg:\n+ maxItems: 1\n+\n+ '#pwm-cells':\n+ const: 3\n+\n+ interrupts:\n+ items:\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.0\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.0\n+ - description: A and B both high interrupt for channel GPT{0,1}.0\n+ - description: A and B both low interrupt for channel GPT{0,1}.0\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.1\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.1\n+ - description: A and B both high interrupt for channel GPT{0,1}.1\n+ - description: A and B both low interrupt for channel GPT{0,1}.1\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.2\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.2\n+ - description: A and B both high interrupt for channel GPT{0,1}.2\n+ - description: A and B both low interrupt for channel GPT{0,1}.2\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.3\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.3\n+ - description: A and B both high interrupt for channel GPT{0,1}.3\n+ - description: A and B both low interrupt for channel GPT{0,1}.3\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.4\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.4\n+ - description: A and B both high interrupt for channel GPT{0,1}.4\n+ - description: A and B both low interrupt for channel GPT{0,1}.4\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.5\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.5\n+ - description: A and B both high interrupt for channel GPT{0,1}.5\n+ - description: A and B both low interrupt for channel GPT{0,1}.5\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.6\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.6\n+ - description: A and B both high interrupt for channel GPT{0,1}.6\n+ - description: A and B both low interrupt for channel GPT{0,1}.6\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.7\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.7\n+ - description: A and B both high interrupt for channel GPT{0,1}.7\n+ - description: A and B both low interrupt for channel GPT{0,1}.7\n+\n+ interrupt-names:\n+ items:\n+ - const: gtcia0\n+ - const: gtcib0\n+ - const: gtcic0\n+ - const: gtcid0\n+ - const: gtcie0\n+ - const: gtcif0\n+ - const: gtcih0\n+ - const: gtcil0\n+ - const: gtcia1\n+ - const: gtcib1\n+ - const: gtcic1\n+ - const: gtcid1\n+ - const: gtcie1\n+ - const: gtcif1\n+ - const: gtcih1\n+ - const: gtcil1\n+ - const: gtcia2\n+ - const: gtcib2\n+ - const: gtcic2\n+ - const: gtcid2\n+ - const: gtcie2\n+ - const: gtcif2\n+ - const: gtcih2\n+ - const: gtcil2\n+ - const: gtcia3\n+ - const: gtcib3\n+ - const: gtcic3\n+ - const: gtcid3\n+ - const: gtcie3\n+ - const: gtcif3\n+ - const: gtcih3\n+ - const: gtcil3\n+ - const: gtcia4\n+ - const: gtcib4\n+ - const: gtcic4\n+ - const: gtcid4\n+ - const: gtcie4\n+ - const: gtcif4\n+ - const: gtcih4\n+ - const: gtcil4\n+ - const: gtcia5\n+ - const: gtcib5\n+ - const: gtcic5\n+ - const: gtcid5\n+ - const: gtcie5\n+ - const: gtcif5\n+ - const: gtcih5\n+ - const: gtcil5\n+ - const: gtcia6\n+ - const: gtcib6\n+ - const: gtcic6\n+ - const: gtcid6\n+ - const: gtcie6\n+ - const: gtcif6\n+ - const: gtcih6\n+ - const: gtcil6\n+ - const: gtcia7\n+ - const: gtcib7\n+ - const: gtcic7\n+ - const: gtcid7\n+ - const: gtcie7\n+ - const: gtcif7\n+ - const: gtcih7\n+ - const: gtcil7\n+\n+ clocks:\n+ items:\n+ - description: Core clock (PCLKD)\n+ - description: Bus clock (PCLKA)\n+\n+ clock-names:\n+ items:\n+ - const: core\n+ - const: bus\n+\n+ power-domains:\n+ maxItems: 1\n+\n+ resets:\n+ items:\n+ - description: Reset for bus clock (PCLKA/PCLKD)\n+ - description: Reset for core clock (PCLKD)\n+\n+ reset-names:\n+ items:\n+ - const: rst_p\n+ - const: rst_s\n+\n+required:\n+ - compatible\n+ - reg\n+ - interrupts\n+ - interrupt-names\n+ - clocks\n+ - clock-names\n+ - power-domains\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: pwm.yaml#\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \n+ #include \n+\n+ pwm@13010000 {\n+ compatible = \"renesas,r9a09g047-gpt\";\n+ reg = <0x13010000 0x10000>;\n+ interrupts = ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ,\n+ ;\n+ interrupt-names = \"gtcia0\", \"gtcib0\", \"gtcic0\", \"gtcid0\",\n+ \"gtcie0\", \"gtcif0\", \"gtcih0\", \"gtcil0\",\n+ \"gtcia1\", \"gtcib1\", \"gtcic1\", \"gtcid1\",\n+ \"gtcie1\", \"gtcif1\", \"gtcih1\", \"gtcil1\",\n+ \"gtcia2\", \"gtcib2\", \"gtcic2\", \"gtcid2\",\n+ \"gtcie2\", \"gtcif2\", \"gtcih2\", \"gtcil2\",\n+ \"gtcia3\", \"gtcib3\", \"gtcic3\", \"gtcid3\",\n+ \"gtcie3\", \"gtcif3\", \"gtcih3\", \"gtcil3\",\n+ \"gtcia4\", \"gtcib4\", \"gtcic4\", \"gtcid4\",\n+ \"gtcie4\", \"gtcif4\", \"gtcih4\", \"gtcil4\",\n+ \"gtcia5\", \"gtcib5\", \"gtcic5\", \"gtcid5\",\n+ \"gtcie5\", \"gtcif5\", \"gtcih5\", \"gtcil5\",\n+ \"gtcia6\", \"gtcib6\", \"gtcic6\", \"gtcid6\",\n+ \"gtcie6\", \"gtcif6\", \"gtcih6\", \"gtcil6\",\n+ \"gtcia7\", \"gtcib7\", \"gtcic7\", \"gtcid7\",\n+ \"gtcie7\", \"gtcif7\", \"gtcih7\", \"gtcil7\";\n+ clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;\n+ clock-names = \"core\", \"bus\";\n+ power-domains = <&cpg>;\n+ resets = <&cpg 0x59>, <&cpg 0x5a>;\n+ reset-names = \"rst_p\", \"rst_s\";\n+ #pwm-cells = <3>;\n+ };\n","prefixes":["v5","8/9"]}