{"id":2225074,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225074/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-8-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104248.86702-8-mohamed@unpredictable.fr>","date":"2026-04-20T10:42:17","name":"[v2,07/38] whpx: i386: introduce proper cpuid support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"656fba509369d2cfd8a1f9efdef1f36f371bbbba","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-8-mohamed@unpredictable.fr/mbox/","series":[{"id":500592,"url":"http://patchwork.ozlabs.org/api/1.1/series/500592/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500592","date":"2026-04-20T10:42:10","name":"WHPX x86 updates for QEMU 11.1","version":2,"mbox":"http://patchwork.ozlabs.org/series/500592/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225074/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225074/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=HdahSLQ1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzhx612x7z1yCv\n\tfor ; Mon, 20 Apr 2026 20:46:18 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEm64-0006ts-DB; Mon, 20 Apr 2026 06:43:20 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEm61-0006tN-I0\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:43:17 -0400","from p-west3-cluster5-host2-snip4-10.eps.apple.com ([57.103.72.83]\n helo=outbound.ms.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEm5z-0000YJ-6B\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:43:16 -0400","from outbound.ms.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPS id\n D5373180045B; Mon, 20 Apr 2026 10:43:11 +0000 (UTC)","from localhost.localdomain (unknown [17.57.154.37])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPSA id\n F344618000BF; Mon, 20 Apr 2026 10:43:08 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776681794; x=1779273794;\n bh=rzH0nfvQx4HDQyGiqHq24GYidgrGqENXmeSSBmYWI5k=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=HdahSLQ1zfFN3gh+ng+3cEn1UkgkUMdxQfeGHE/bhKxDSvYRQocB8nUaeMMhIPt7OB3TezKOIG9NlM/DguZ6ma0rNBf1LITMWMBBEnM/4SrEAeBNfGkDErQ14PaRmncezsjxLHRTGfCJVE2KBo9tURmEVqpoNEOkP3f5pQuhnXYZhqEuz0x49PjJ7Bn4H7FQ+8GhHp/6VLOtQxpxJ6ffFK/C3WYiDeMPt6DA1xQkmL8/QE4pntM6FIE6Cki/7qSdCn8rc/x87DIJyYbehYZLNOt8/Ju3iX753LDmIUtIk3GF6upZXP8OSoc2Lt7pycTfJovGOil5H3TBXh1t+eidoA==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org, Mohamed Mediouni ,\n Paolo Bonzini ,\n Phil Dennis-Jordan ,\n Roman Bolshakov ,\n Pierrick Bouvier ,\n Pedro Barbuda , Wei Liu ,\n \"Michael S. Tsirkin\" ,\n Peter Maydell , Zhao Liu ","Subject":"[PATCH v2 07/38] whpx: i386: introduce proper cpuid support","Date":"Mon, 20 Apr 2026 12:42:17 +0200","Message-ID":"<20260420104248.86702-8-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260420104248.86702-1-mohamed@unpredictable.fr>","References":"<20260420104248.86702-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"vu_J19aCgQGVGpabYkC0JeAqTSqn076t","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIwMDEwNCBTYWx0ZWRfX0e7DAY3dG/+c\n gCopN9cDCM8nxw2YexQT1jtv5Io3pj29IYT+wje1Bb4m0WPpM/pFzVo5BUwSUZ/wtcqyYsk9oNr\n dZK3+pPyVpa2r+T5upXEz7rZdtbZ2ZEBOMWhTB3f7+s/11/rJeF/a3/yNCtH8S6YqmoAx0uUzS0\n 6ibA4u131UTq62PMqnMMC4Ba76Prmp47099hoQLU9A53kRvcqGU2jHjYGGjwFpd/ObV2/cgMKta\n qZ9EcVe+lHrmmw/MqzX2SNIBZPJsEho3cV7PxV7d/otADBYZNWK2+RKiR5EBWfrSu5CQwJECNrn\n 6hAHOL9xEByp2od5vJ6JxM9IBQab5Eke9SS4CDOYNe+teoSgiAyOrQE3UcctvA=","X-Authority-Info-Out":"v=2.4 cv=LaIxKzfi c=1 sm=1 tr=0 ts=69e60341\n cx=c_apl:c_pps:t_out a=qkKslKyYc0ctBTeLUVfTFg==:117 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=n8cRCUxqL_yedgTzvKUA:9","X-Proofpoint-GUID":"vu_J19aCgQGVGpabYkC0JeAqTSqn076t","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_02,2026-04-17_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0\n lowpriorityscore=0 adultscore=0 spamscore=0 mlxlogscore=999 clxscore=1030\n suspectscore=0 phishscore=0 mlxscore=0 malwarescore=0 bulkscore=0\n classifier=spam authscore=0 adjust=0 reason=mlx scancount=1\n engine=8.22.0-2601150000 definitions=main-2604200104","Received-SPF":"pass client-ip=57.103.72.83;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Unlike the implementation in QEMU 10.2, this one works.\n\nIt's not optimal though as it doesn't use the Hyper-V support for this.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 123 ++++++++++++++++++++++++++++++++++--\n 1 file changed, 119 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex c2a78312f8..53b59a98b9 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -2071,6 +2071,7 @@ int whpx_vcpu_run(CPUState *cpu)\n WHV_REGISTER_NAME reg_names[5];\n UINT32 reg_count = 5;\n X86CPU *x86_cpu = X86_CPU(cpu);\n+ X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);\n CPUX86State *env = &x86_cpu->env;\n \n reg_names[0] = WHvX64RegisterRip;\n@@ -2083,7 +2084,15 @@ int whpx_vcpu_run(CPUState *cpu)\n vcpu->exit_ctx.VpContext.Rip +\n vcpu->exit_ctx.VpContext.InstructionLength;\n \n- if (whpx_is_legacy_os()) {\n+ /*\n+ * On Windows 10 we can't query features from\n+ * the Hyper-V interface.\n+ *\n+ * On Windows 11, if using xcc->max_features\n+ * just pass through what the hypervisor\n+ * provides without any QEMU filtering.\n+ */\n+ if (whpx_is_legacy_os() || xcc->max_features) {\n reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;\n reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;\n reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;\n@@ -2135,6 +2144,60 @@ int whpx_vcpu_run(CPUState *cpu)\n }\n break;\n }\n+ } else {\n+ switch (vcpu->exit_ctx.CpuidAccess.Rax) {\n+ case 0x40000000:\n+ case 0x40000001:\n+ case 0x40000010:\n+ reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;\n+ reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;\n+ reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;\n+ reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;\n+ break;\n+ }\n+ }\n+\n+ if (vcpu->exit_ctx.CpuidAccess.Rax == 0x1) {\n+ if (cpu_has_x2apic_feature(env)) {\n+ reg_values[2].Reg64 |= CPUID_EXT_X2APIC;\n+ } else {\n+ reg_values[2].Reg32 &= ~CPUID_EXT_X2APIC;\n+ }\n+ }\n+\n+ /* Dynamic depending on XCR0 and XSS, so query DefaultResult */\n+ if (vcpu->exit_ctx.CpuidAccess.Rax == 0x07\n+ && vcpu->exit_ctx.CpuidAccess.Rcx == 0) {\n+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRdx\n+ & CPUID_7_0_EDX_CET_IBT) {\n+ reg_values[3].Reg32 |= CPUID_7_0_EDX_CET_IBT;\n+ } else {\n+ reg_values[3].Reg32 &= ~CPUID_7_0_EDX_CET_IBT;\n+ }\n+\n+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx\n+ & CPUID_7_0_ECX_CET_SHSTK) {\n+ reg_values[2].Reg32 |= CPUID_7_0_ECX_CET_SHSTK;\n+ } else {\n+ reg_values[2].Reg32 &= ~CPUID_7_0_ECX_CET_SHSTK;\n+ }\n+\n+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx\n+ & CPUID_7_0_ECX_OSPKE) {\n+ reg_values[2].Reg32 |= CPUID_7_0_ECX_OSPKE;\n+ } else {\n+ reg_values[2].Reg32 &= ~CPUID_7_0_ECX_OSPKE;\n+ }\n+ }\n+\n+ /* OSXSAVE is dynamic. Do this instead of syncing CR4 */\n+ if (vcpu->exit_ctx.CpuidAccess.Rax == 1) {\n+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx\n+ & CPUID_EXT_OSXSAVE) {\n+ reg_values[2].Reg32 |= CPUID_EXT_OSXSAVE;\n+ } else {\n+ reg_values[2].Reg32 &= ~CPUID_EXT_OSXSAVE;\n+ }\n }\n \n hr = whp_dispatch.WHvSetVirtualProcessorRegisters(\n@@ -2324,6 +2387,45 @@ error:\n return ret;\n }\n \n+static void whpx_cpu_xsave_init(void)\n+{\n+ static bool first = true;\n+ int i;\n+\n+ if (!first) {\n+ return;\n+ }\n+ first = false;\n+\n+ /* x87 and SSE states are in the legacy region of the XSAVE area. */\n+ x86_ext_save_areas[XSTATE_FP_BIT].offset = 0;\n+ x86_ext_save_areas[XSTATE_SSE_BIT].offset = 0;\n+\n+ for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {\n+ ExtSaveArea *esa = &x86_ext_save_areas[i];\n+\n+ if (esa->size) {\n+ int sz = whpx_get_supported_cpuid(0xd, i, R_EAX);\n+ if (sz != 0) {\n+ assert(esa->size == sz);\n+ esa->offset = whpx_get_supported_cpuid(0xd, i, R_EBX);\n+ }\n+ }\n+ }\n+}\n+\n+static void whpx_cpu_max_instance_init(X86CPU *cpu)\n+{\n+ CPUX86State *env = &cpu->env;\n+\n+ env->cpuid_min_level =\n+ whpx_get_supported_cpuid(0x0, 0, R_EAX);\n+ env->cpuid_min_xlevel =\n+ whpx_get_supported_cpuid(0x80000000, 0, R_EAX);\n+ env->cpuid_min_xlevel2 =\n+ whpx_get_supported_cpuid(0xC0000000, 0, R_EAX);\n+}\n+\n static PropValue whpx_default_props[] = {\n { \"x2apic\", \"on\" },\n { NULL, NULL },\n@@ -2333,9 +2435,18 @@ static PropValue whpx_default_props[] = {\n void whpx_cpu_instance_init(CPUState *cs)\n {\n X86CPU *cpu = X86_CPU(cs);\n+ X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);\n \n host_cpu_instance_init(cpu);\n x86_cpu_apply_props(cpu, whpx_default_props);\n+\n+ if (!whpx_is_legacy_os() && xcc->max_features) {\n+ whpx_cpu_max_instance_init(cpu);\n+ }\n+\n+ if (!whpx_is_legacy_os()) {\n+ whpx_cpu_xsave_init();\n+ }\n }\n \n /*\n@@ -2353,8 +2464,12 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n WHV_CAPABILITY_FEATURES features = {0};\n WHV_PROCESSOR_FEATURES_BANKS processor_features;\n WHV_PROCESSOR_PERFMON_FEATURES perfmon_features;\n- UINT32 cpuidExitList[] = {1};\n- UINT32 cpuidExitList_nohyperv[] = {1, 0x40000000, 0x40000001, 0x40000010};\n+\n+ UINT32 cpuidExitList[] = {0x0, 0x1, 0x6, 0x7, 0x14, 0x24, 0x29, 0x1E,\n+ 0x40000000, 0x40000001, 0x40000010, 0x80000000, 0x80000001,\n+ 0x80000002, 0x80000003, 0x80000004, 0x80000007, 0x80000008,\n+ 0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001};\n+ UINT32 cpuidExitList_legacy_os[] = {1, 0x40000000, 0x40000001, 0x40000010};\n \n whpx = &whpx_global;\n \n@@ -2610,7 +2725,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\n WHvPartitionPropertyCodeCpuidExitList,\n- whpx->hyperv_enlightenments_enabled ? cpuidExitList : cpuidExitList_nohyperv,\n+ !whpx_is_legacy_os() ? cpuidExitList : cpuidExitList_legacy_os,\n RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));\n \n if (FAILED(hr)) {\n","prefixes":["v2","07/38"]}