{"id":2225062,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225062/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-3-biju.das.jz@bp.renesas.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104332.153640-3-biju.das.jz@bp.renesas.com>","date":"2026-04-20T10:43:19","name":"[v5,2/9] pwm: rzg2l-gpt: Add support for gpt linking with poeg","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c7560678f3a4d264931d0ab931c8b1068abcd918","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-3-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":500593,"url":"http://patchwork.ozlabs.org/api/1.1/series/500593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593","date":"2026-04-20T10:43:17","name":"Add Renesas RZ/G3E GPT support","version":5,"mbox":"http://patchwork.ozlabs.org/series/500593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225062/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225062/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=VUADfpue;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"From: Biju Das \n\nThe General PWM Timer (GPT) is capable of detecting \"dead time error\nand short-circuits between output pins\" and send Output disable\nrequest to poeg(Port Output Enable for GPT).\n\nAdd support for linking poeg group with gpt, so that gpt can control\nthe output disable function by adding rzg2l_gpt_poeg_init() to parse\nthe renesas,poegs device tree property and establish links between POEG\ngroups (A–D) and GPT hardware channels (0–7). For each valid, enabled\nPOEG phandle entry, the driver:\n - Reads the renesas,poeg-id from the POEG node and validates it against\n the supported range\n - Records the GPT–POEG association in a per-chip bitmap (poeg_gpt_link)\n - Configures GTINTAD to route the output disable request to the correct\n POEG group\n - Configures GTIOR (OADF/OBDF fields) to set both output pins to\n high-impedance on an output disable event\n\nNon-enabled POEG nodes are silently skipped.\n\nSigned-off-by: Biju Das \n---\nv5:\n * Updated commit description.\n * Replaced return type of rzg2l_gpt_poeg_init() from void->int and\n probe() checks this return value.\n * Added more error checks in rzg2l_gpt_poeg_init() \nV24 from [1]:\n[1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.renesas.com/\n---\n drivers/pwm/pwm-rzg2l-gpt.c | 93 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 93 insertions(+)","diff":"diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\nindex 4856af080e8e..71ae2f891fd2 100644\n--- a/drivers/pwm/pwm-rzg2l-gpt.c\n+++ b/drivers/pwm/pwm-rzg2l-gpt.c\n@@ -39,6 +39,7 @@\n #define RZG2L_GTCR(ch)\t\t(0x2c + RZG2L_GET_CH_OFFS(ch))\n #define RZG2L_GTUDDTYC(ch)\t(0x30 + RZG2L_GET_CH_OFFS(ch))\n #define RZG2L_GTIOR(ch)\t\t(0x34 + RZG2L_GET_CH_OFFS(ch))\n+#define RZG2L_GTINTAD(ch)\t(0x38 + RZG2L_GET_CH_OFFS(ch))\n #define RZG2L_GTBER(ch)\t\t(0x40 + RZG2L_GET_CH_OFFS(ch))\n #define RZG2L_GTCNT(ch)\t\t(0x48 + RZG2L_GET_CH_OFFS(ch))\n #define RZG2L_GTCCR(ch, sub_ch)\t(0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_ch))\n@@ -55,12 +56,19 @@\n #define RZG2L_GTUDDTYC_UP_COUNTING\t(RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)\n \n #define RZG2L_GTIOR_GTIOA\tGENMASK(4, 0)\n+#define RZG2L_GTIOR_OADF\tGENMASK(10, 9)\n #define RZG2L_GTIOR_GTIOB\tGENMASK(20, 16)\n+#define RZG2L_GTIOR_OBDF\tGENMASK(26, 25)\n #define RZG2L_GTIOR_GTIOx(sub_ch)\t((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GTIOR_GTIOA)\n #define RZG2L_GTIOR_OAE\t\tBIT(8)\n #define RZG2L_GTIOR_OBE\t\tBIT(24)\n #define RZG2L_GTIOR_OxE(sub_ch)\t\t((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR_OAE)\n \n+#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE\tBIT(9)\n+#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE\tBIT(25)\n+#define RZG2L_GTIOR_PIN_DISABLE_SETTING \\\n+\t(RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE)\n+\n #define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE\t0x1b\n #define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \\\n \t(RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE)\n@@ -71,12 +79,17 @@\n \t((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \\\n \t RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH)\n \n+#define RZG2L_GTINTAD_GRP_MASK\tGENMASK(25, 24)\n+\n #define RZG2L_MAX_HW_CHANNELS\t8\n #define RZG2L_CHANNELS_PER_IO\t2\n #define RZG2L_MAX_PWM_CHANNELS\t(RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)\n #define RZG2L_MAX_SCALE_FACTOR\t1024\n #define RZG2L_MAX_TICKS\t\t((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)\n \n+#define RZG2L_MAX_POEG_GROUPS\t4\n+#define RZG2L_LAST_POEG_GROUP\t3\n+\n struct rzg2l_gpt_chip {\n \tvoid __iomem *mmio;\n \tstruct mutex lock; /* lock to protect shared channel resources */\n@@ -84,6 +97,7 @@ struct rzg2l_gpt_chip {\n \tu32 period_ticks[RZG2L_MAX_HW_CHANNELS];\n \tu32 channel_request_count[RZG2L_MAX_HW_CHANNELS];\n \tu32 channel_enable_count[RZG2L_MAX_HW_CHANNELS];\n+\tDECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);\n };\n \n static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)\n@@ -375,6 +389,81 @@ static const struct pwm_ops rzg2l_gpt_ops = {\n \t.apply = rzg2l_gpt_apply,\n };\n \n+/*\n+ * This function links a poeg group{A,B,C,D} with a gpt channel{0..7} and\n+ * configure the pin for output disable.\n+ */\n+static int rzg2l_gpt_poeg_init(struct platform_device *pdev,\n+\t\t\t struct rzg2l_gpt_chip *rzg2l_gpt)\n+{\n+\tconst char *poeg_name = \"renesas,poegs\";\n+\tstruct of_phandle_args of_args;\n+\tstruct property *poegs;\n+\tunsigned int i;\n+\tu32 poeg_grp;\n+\tu32 bitpos;\n+\tint cells;\n+\tint ret;\n+\n+\tpoegs = of_find_property(pdev->dev.of_node, poeg_name, NULL);\n+\tif (!poegs)\n+\t\treturn 0;\n+\n+\tcells = of_property_count_u32_elems(pdev->dev.of_node, poeg_name);\n+\tif (cells < 0)\n+\t\treturn cells;\n+\n+\tif (cells & 1)\n+\t\treturn -EINVAL;\n+\n+\tcells >>= 1;\n+\tfor (i = 0; i < cells; i++) {\n+\t\tret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,\n+\t\t\t\t\t\t poeg_name, 1, i,\n+\t\t\t\t\t\t &of_args);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (of_args.args[0] >= RZG2L_MAX_HW_CHANNELS) {\n+\t\t\tdev_err(&pdev->dev, \"Invalid channel %d >= %d\\n\",\n+\t\t\t\tof_args.args[0], RZG2L_MAX_HW_CHANNELS);\n+\t\t\tgoto err_of_node;\n+\t\t}\n+\n+\t\tif (!of_device_is_available(of_args.np)) {\n+\t\t\t/* It's fine to have a phandle to a non-enabled poeg. */\n+\t\t\tof_node_put(of_args.np);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (!of_property_read_u32(of_args.np, \"renesas,poeg-id\", &poeg_grp)) {\n+\t\t\tif (poeg_grp > RZG2L_LAST_POEG_GROUP) {\n+\t\t\t\tdev_err(&pdev->dev, \"Invalid poeg group %d > %d\\n\",\n+\t\t\t\t\tpoeg_grp, RZG2L_LAST_POEG_GROUP);\n+\t\t\t\tgoto err_of_node;\n+\t\t\t}\n+\n+\t\t\tbitpos = of_args.args[0] + poeg_grp * RZG2L_MAX_HW_CHANNELS;\n+\t\t\tset_bit(bitpos, rzg2l_gpt->poeg_gpt_link);\n+\n+\t\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTINTAD(of_args.args[0]),\n+\t\t\t\t\t RZG2L_GTINTAD_GRP_MASK, poeg_grp << 24);\n+\n+\t\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(of_args.args[0]),\n+\t\t\t\t\t RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF,\n+\t\t\t\t\t RZG2L_GTIOR_PIN_DISABLE_SETTING);\n+\t\t}\n+\n+\t\tof_node_put(of_args.np);\n+\t}\n+\n+\treturn 0;\n+\n+err_of_node:\n+\tof_node_put(of_args.np);\n+\treturn -EINVAL;\n+}\n+\n static int rzg2l_gpt_probe(struct platform_device *pdev)\n {\n \tstruct rzg2l_gpt_chip *rzg2l_gpt;\n@@ -426,6 +515,10 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \tif (rzg2l_gpt->rate_khz * KILO != rate)\n \t\treturn dev_err_probe(dev, -EINVAL, \"Rate is not multiple of 1000\");\n \n+\tret = rzg2l_gpt_poeg_init(pdev, rzg2l_gpt);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to link gpt with poeg\\n\");\n+\n \tmutex_init(&rzg2l_gpt->lock);\n \n \tchip->ops = &rzg2l_gpt_ops;\n","prefixes":["v5","2/9"]}