{"id":2225043,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2225043/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260420100601.343707-3-pshete@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260420100601.343707-3-pshete@nvidia.com>","date":"2026-04-20T10:05:57","name":"[v2,2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"95762a3feacb13f88399f0c5fb6e0cdffc0906c9","submitter":{"id":82424,"url":"http://patchwork.ozlabs.org/api/1.1/people/82424/?format=json","name":"Prathamesh Shete","email":"pshete@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260420100601.343707-3-pshete@nvidia.com/mbox/","series":[{"id":500585,"url":"http://patchwork.ozlabs.org/api/1.1/series/500585/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500585","date":"2026-04-20T10:05:56","name":"Add Tegra238 and Tegra264 pinctrl support","version":2,"mbox":"http://patchwork.ozlabs.org/series/500585/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225043/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225043/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=lpWbPZHi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Document their\ncompatible strings and describe the list of pins and\nfunctions that they provide.\n\nSigned-off-by: Prathamesh Shete \n---\nChanges in v2:\n - Add a 'required:' block listing 'compatible' and 'reg'.\n - Switch top-level 'unevaluatedProperties: false' to\n 'additionalProperties: false'.\n---\n .../pinctrl/nvidia,tegra238-pinmux-aon.yaml | 82 +++++++\n .../nvidia,tegra238-pinmux-common.yaml | 73 ++++++\n .../pinctrl/nvidia,tegra238-pinmux.yaml | 219 ++++++++++++++++++\n 3 files changed, 374 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml\nnew file mode 100644\nindex 000000000000..ab9264d87c88\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml\n@@ -0,0 +1,82 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra238 AON Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding \n+ - Jon Hunter \n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra238-pinmux-aon\n+\n+ reg:\n+ maxItems: 1\n+\n+patternProperties:\n+ \"^pinmux(-[a-z0-9-]+)?$\":\n+ type: object\n+\n+ # pin groups\n+ additionalProperties:\n+ $ref: nvidia,tegra238-pinmux-common.yaml\n+\n+ properties:\n+ nvidia,pins:\n+ items:\n+ enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,\n+ pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,\n+ soc_gpio25_paa6, soc_gpio26_paa7,\n+ hdmi_cec_pbb0,\n+ spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,\n+ spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,\n+ uart3_rx_pcc6, gen2_i2c_scl_pcc7,\n+ gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,\n+ gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,\n+ dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,\n+ pwm3_pee0, pwm7_pee1,\n+ # drive groups (ordered PAA, PBB, PCC, PDD, PEE)\n+ drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,\n+ drive_vcomp_alert_paa2, drive_pwm1_paa3,\n+ drive_batt_oc_paa4, drive_soc_gpio04_paa5,\n+ drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,\n+ drive_hdmi_cec_pbb0,\n+ drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,\n+ drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,\n+ drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,\n+ drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,\n+ drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,\n+ drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,\n+ drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,\n+ drive_soc_gpio19_pdd6, drive_pwm2_pdd7,\n+ drive_pwm3_pee0, drive_pwm7_pee1 ]\n+\n+required:\n+ - compatible\n+ - reg\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ pinmux@c300000 {\n+ compatible = \"nvidia,tegra238-pinmux-aon\";\n+ reg = <0x0c300000 0x4000>;\n+\n+ pinctrl-names = \"cec\";\n+ pinctrl-0 = <&cec_state>;\n+\n+ cec_state: pinmux-cec {\n+ cec {\n+ nvidia,pins = \"hdmi_cec_pbb0\";\n+ nvidia,function = \"hdmi_cec\";\n+ };\n+ };\n+ };\n+...\ndiff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml\nnew file mode 100644\nindex 000000000000..5c7608981f2d\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml\n@@ -0,0 +1,73 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra238 Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding \n+ - Jon Hunter \n+\n+$ref: nvidia,tegra-pinmux-common.yaml\n+\n+properties:\n+ nvidia,function:\n+ enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat,\n+ i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0,\n+ usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din,\n+ spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout,\n+ gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat,\n+ i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat,\n+ dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd,\n+ i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd,\n+ uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk,\n+ i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk,\n+ i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk,\n+ i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk,\n+ i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out,\n+ pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l,\n+ pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l,\n+ dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n,\n+ uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk,\n+ sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2,\n+ sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec,\n+ gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk,\n+ spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din,\n+ ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0,\n+ ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd,\n+ uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7,\n+ gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat,\n+ rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8,\n+ nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux,\n+ dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat,\n+ dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk,\n+ i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in,\n+ sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk,\n+ ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n,\n+ ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso,\n+ spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0,\n+ spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat,\n+ dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3,\n+ tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3,\n+ sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b,\n+ tsc_edge_out0c, soc_therm_oc2 ]\n+\n+ # out of the common properties, only these are allowed for Tegra238\n+ nvidia,pins: true\n+ nvidia,pull: true\n+ nvidia,tristate: true\n+ nvidia,schmitt: true\n+ nvidia,enable-input: true\n+ nvidia,open-drain: true\n+ nvidia,lock: true\n+ nvidia,drive-type: true\n+ nvidia,io-hv: true\n+\n+required:\n+ - nvidia,pins\n+\n+additionalProperties: false\n+\n+...\ndiff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml\nnew file mode 100644\nindex 000000000000..92d276634d76\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml\n@@ -0,0 +1,219 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra238 Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding \n+ - Jon Hunter \n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra238-pinmux\n+\n+ reg:\n+ maxItems: 1\n+\n+patternProperties:\n+ \"^pinmux(-[a-z0-9-]+)?$\":\n+ type: object\n+\n+ # pin groups\n+ additionalProperties:\n+ $ref: nvidia,tegra238-pinmux-common.yaml\n+\n+ properties:\n+ nvidia,pins:\n+ items:\n+ enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3,\n+ spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7,\n+ spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3,\n+ spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1,\n+ extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4,\n+ cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7,\n+ soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2,\n+ soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5,\n+ soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0,\n+ uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3,\n+ soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2,\n+ soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5,\n+ soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0,\n+ soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3,\n+ uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6,\n+ soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1,\n+ gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4,\n+ soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1,\n+ dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4,\n+ soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7,\n+ soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2,\n+ soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1,\n+ qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4,\n+ soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7,\n+ soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2,\n+ soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5,\n+ soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0,\n+ uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0,\n+ soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3,\n+ dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7,\n+ soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2,\n+ soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2,\n+ soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5,\n+ soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0,\n+ gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3,\n+ gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6,\n+ gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1,\n+ soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4,\n+ soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7,\n+ sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2,\n+ sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5,\n+ ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0,\n+ pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2,\n+ pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4,\n+ pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6,\n+ pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1,\n+ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,\n+ pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,\n+ soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0,\n+ spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,\n+ spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,\n+ uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,\n+ gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3,\n+ dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6,\n+ pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,\n+ soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,\n+ soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,\n+ soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,\n+ soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,\n+ soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,\n+ uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,\n+ uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,\n+ uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp,\n+ # drive groups\n+ drive_soc_gpio36_pt1, drive_soc_gpio53_pt2,\n+ drive_soc_gpio38_pt3, drive_soc_gpio40_pt4,\n+ drive_soc_gpio75_ps2, drive_soc_gpio81_pt0,\n+ drive_soc_gpio78_ps5, drive_soc_gpio34_pt5,\n+ drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4,\n+ drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0,\n+ drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6,\n+ drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7,\n+ drive_soc_gpio61_pr0, drive_soc_gpio62_pr1,\n+ drive_soc_gpio63_pr2, drive_soc_gpio64_pr3,\n+ drive_soc_gpio65_pr4, drive_soc_gpio66_pr5,\n+ drive_soc_gpio67_pr6, drive_soc_gpio68_pr7,\n+ drive_spi3_miso_pa4, drive_spi1_cs0_pb3,\n+ drive_spi3_cs0_pa6, drive_spi1_miso_pb1,\n+ drive_spi3_cs1_pa7, drive_spi1_sck_pb0,\n+ drive_spi3_sck_pa3, drive_spi1_cs1_pb4,\n+ drive_spi1_mosi_pb2, drive_spi3_mosi_pa5,\n+ drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1,\n+ drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3,\n+ drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5,\n+ drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6,\n+ drive_soc_gpio24_pc7, drive_soc_gpio27_pd0,\n+ drive_soc_gpio29_pd2, drive_soc_gpio32_pd4,\n+ drive_soc_gpio33_pd3, drive_soc_gpio35_pd5,\n+ drive_soc_gpio37_pd6, drive_soc_gpio56_pd7,\n+ drive_soc_gpio55_pd1, drive_uart1_cts_pe3,\n+ drive_uart1_rts_pe2, drive_uart1_rx_pe1,\n+ drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0,\n+ drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4,\n+ drive_uart4_cts_pg5, drive_uart4_rts_pg4,\n+ drive_uart4_rx_pg3, drive_uart4_tx_pg2,\n+ drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3,\n+ drive_soc_gpio20_pf6, drive_soc_gpio21_pf7,\n+ drive_soc_gpio22_pg0, drive_soc_gpio13_pf0,\n+ drive_soc_gpio14_pf1, drive_soc_gpio15_pf2,\n+ drive_soc_gpio16_pf3, drive_soc_gpio17_pf4,\n+ drive_soc_gpio18_pf5, drive_soc_gpio41_pg6,\n+ drive_soc_gpio42_pg7, drive_soc_gpio43_ph0,\n+ drive_soc_gpio44_ph1, drive_soc_gpio06_pg1,\n+ drive_soc_gpio07_ph5, drive_dap4_sclk_pp4,\n+ drive_dap4_dout_pp5, drive_dap4_din_pp6,\n+ drive_dap4_fs_pp7, drive_soc_gpio167_pp0,\n+ drive_soc_gpio168_pp1, drive_soc_gpio169_pp2,\n+ drive_soc_gpio170_pp3, drive_soc_gpio171_pq0,\n+ drive_soc_gpio172_pq1, drive_soc_gpio173_pq2,\n+ drive_soc_gpio45_pk0, drive_soc_gpio46_pk1,\n+ drive_soc_gpio47_pk2, drive_soc_gpio48_pk3,\n+ drive_soc_gpio57_pj4, drive_soc_gpio58_pj5,\n+ drive_soc_gpio59_pj6, drive_soc_gpio60_pj7,\n+ drive_dap3_fs_pj3, drive_dap3_clk_pj0,\n+ drive_dap3_din_pj2, drive_dap3_dout_pj1,\n+ drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0,\n+ drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3,\n+ drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1,\n+ drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6,\n+ drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1,\n+ drive_qspi0_io0_pl1, drive_qspi0_io1_pl2,\n+ drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3,\n+ drive_soc_gpio156_pm0, drive_soc_gpio155_pl7,\n+ drive_soc_gpio160_pm4, drive_soc_gpio154_pl6,\n+ drive_soc_gpio152_pl4, drive_soc_gpio153_pl5,\n+ drive_soc_gpio161_pm5, drive_soc_gpio162_pm6,\n+ drive_soc_gpio159_pm3, drive_soc_gpio157_pm1,\n+ drive_soc_gpio158_pm2, drive_uart7_cts_pn2,\n+ drive_uart7_rts_pn1, drive_uart7_tx_pm7,\n+ drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0,\n+ drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5,\n+ drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3,\n+ drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1,\n+ drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4,\n+ drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2,\n+ drive_hdmi_cec_pbb0, drive_touch_clk_pdd3,\n+ drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,\n+ drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,\n+ drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,\n+ drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,\n+ drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,\n+ drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,\n+ drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,\n+ drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,\n+ drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6,\n+ drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,\n+ drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,\n+ drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,\n+ drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,\n+ drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6,\n+ drive_soc_gpio69_pff0, drive_soc_gpio25_paa6,\n+ drive_soc_gpio26_paa7, drive_uart5_tx_pgg7,\n+ drive_uart5_rx_phh0, drive_uart2_tx_pgg2,\n+ drive_uart2_rx_pgg3, drive_uart2_cts_pgg5,\n+ drive_uart2_rts_pgg4, drive_uart5_cts_phh2,\n+ drive_uart5_rts_phh1, drive_pwm7_pee1,\n+ drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3,\n+ drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4,\n+ drive_dmic1_dat_pdd5, drive_sdmmc1_comp ]\n+\n+required:\n+ - compatible\n+ - reg\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ pinmux@2430000 {\n+ compatible = \"nvidia,tegra238-pinmux\";\n+ reg = <0x2430000 0x17000>;\n+\n+ pinctrl-names = \"pex_rst\";\n+ pinctrl-0 = <&pex_rst_c5_out_state>;\n+\n+ pex_rst_c5_out_state: pinmux-pex-rst-c5-out {\n+ pexrst {\n+ nvidia,pins = \"pex_l3_rst_n_pw7\";\n+ nvidia,schmitt = ;\n+ nvidia,enable-input = ;\n+ nvidia,io-hv = ;\n+ nvidia,tristate = ;\n+ nvidia,pull = ;\n+ };\n+ };\n+ };\n+...\n","prefixes":["v2","2/6"]}