{"id":2224896,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2224896/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260419130139.15554-4-alexander@mihalicyn.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260419130139.15554-4-alexander@mihalicyn.com>","date":"2026-04-19T13:01:34","name":"[v6,3/8] hw/nvme: split nvme_init_sq/nvme_init_cq into helpers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"068882ac25dd8c3022f649eb11140ff6c50242fc","submitter":{"id":81630,"url":"http://patchwork.ozlabs.org/api/1.1/people/81630/?format=json","name":"Alexander Mikhalitsyn","email":"alexander@mihalicyn.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260419130139.15554-4-alexander@mihalicyn.com/mbox/","series":[{"id":500500,"url":"http://patchwork.ozlabs.org/api/1.1/series/500500/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500500","date":"2026-04-19T13:01:32","name":"hw/nvme: add basic live migration support","version":6,"mbox":"http://patchwork.ozlabs.org/series/500500/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224896/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224896/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n secure) header.d=mihalicyn.com header.i=@mihalicyn.com header.a=rsa-sha256\n header.s=mihalicyn header.b=KOInC/Wr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alexander Mikhalitsyn \n\nSigned-off-by: Alexander Mikhalitsyn \n---\n hw/nvme/ctrl.c | 59 +++++++++++++++++++++++++++++++-------------------\n 1 file changed, 37 insertions(+), 22 deletions(-)","diff":"diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c\nindex 9f9c9bcbead..191398e700f 100644\n--- a/hw/nvme/ctrl.c\n+++ b/hw/nvme/ctrl.c\n@@ -4854,18 +4854,14 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)\n return NVME_SUCCESS;\n }\n \n-static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,\n- uint16_t sqid, uint16_t cqid, uint16_t size)\n+static void __nvme_init_sq(NvmeSQueue *sq)\n {\n+ NvmeCtrl *n = sq->ctrl;\n+ uint16_t sqid = sq->sqid;\n+ uint16_t cqid = sq->cqid;\n int i;\n NvmeCQueue *cq;\n \n- sq->ctrl = n;\n- sq->dma_addr = dma_addr;\n- sq->sqid = sqid;\n- sq->size = size;\n- sq->cqid = cqid;\n- sq->head = sq->tail = 0;\n sq->io_req = g_new0(NvmeRequest, sq->size);\n \n QTAILQ_INIT(&sq->req_list);\n@@ -4895,6 +4891,18 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,\n n->sq[sqid] = sq;\n }\n \n+static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,\n+ uint16_t sqid, uint16_t cqid, uint16_t size)\n+{\n+ sq->ctrl = n;\n+ sq->dma_addr = dma_addr;\n+ sq->sqid = sqid;\n+ sq->size = size;\n+ sq->cqid = cqid;\n+ sq->head = sq->tail = 0;\n+ __nvme_init_sq(sq);\n+}\n+\n static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req)\n {\n NvmeSQueue *sq;\n@@ -5555,25 +5563,16 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req)\n return NVME_SUCCESS;\n }\n \n-static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,\n- uint16_t cqid, uint16_t vector, uint16_t size,\n- uint16_t irq_enabled)\n+static void __nvme_init_cq(NvmeCQueue *cq)\n {\n+ NvmeCtrl *n = cq->ctrl;\n PCIDevice *pci = PCI_DEVICE(n);\n+ uint16_t cqid = cq->cqid;\n \n- if (msix_enabled(pci) && irq_enabled) {\n- msix_vector_use(pci, vector);\n+ if (msix_enabled(pci) && cq->irq_enabled) {\n+ msix_vector_use(pci, cq->vector);\n }\n \n- cq->ctrl = n;\n- cq->cqid = cqid;\n- cq->size = size;\n- cq->dma_addr = dma_addr;\n- cq->phase = 1;\n- cq->irq_enabled = irq_enabled;\n- cq->vector = vector;\n- cq->head = cq->tail = 0;\n- QTAILQ_INIT(&cq->req_list);\n QTAILQ_INIT(&cq->sq_list);\n if (n->dbbuf_enabled) {\n cq->db_addr = n->dbbuf_dbs + (cqid << 3) + (1 << 2);\n@@ -5590,6 +5589,22 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,\n &DEVICE(cq->ctrl)->mem_reentrancy_guard);\n }\n \n+static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,\n+ uint16_t cqid, uint16_t vector, uint16_t size,\n+ uint16_t irq_enabled)\n+{\n+ cq->ctrl = n;\n+ cq->cqid = cqid;\n+ cq->size = size;\n+ cq->dma_addr = dma_addr;\n+ cq->phase = 1;\n+ cq->irq_enabled = irq_enabled;\n+ cq->vector = vector;\n+ cq->head = cq->tail = 0;\n+ QTAILQ_INIT(&cq->req_list);\n+ __nvme_init_cq(cq);\n+}\n+\n static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)\n {\n NvmeCQueue *cq;\n","prefixes":["v6","3/8"]}