{"id":2223766,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223766/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com/","project":{"id":57,"url":"http://patchwork.ozlabs.org/api/1.1/projects/57/?format=json","name":"Linux ASPEED SoC development","link_name":"linux-aspeed","list_id":"linux-aspeed.lists.ozlabs.org","list_email":"linux-aspeed@lists.ozlabs.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com>","date":"2026-04-16T07:29:44","name":"[v7,2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0ee4951c87e9a845b0040fe456939aa88d5bfbc2","submitter":{"id":80235,"url":"http://patchwork.ozlabs.org/api/1.1/people/80235/?format=json","name":"Billy Tsai","email":"billy_tsai@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com/mbox/","series":[{"id":500090,"url":"http://patchwork.ozlabs.org/api/1.1/series/500090/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=500090","date":"2026-04-16T07:29:42","name":"pinctrl: aspeed: Add AST2700 SoC0 support","version":7,"mbox":"http://patchwork.ozlabs.org/series/500090/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223766/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223766/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed+bounces-3923-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=none smtp.remote-ip=211.20.114.72","lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com","lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com\n (client-ip=211.20.114.72; helo=twmbx01.aspeedtech.com;\n envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org)"],"Received":["from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:21b9:f100::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1 raw public key)\n server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fx8ny2nHqz1yDF\n\tfor ; Thu, 16 Apr 2026 17:31:18 +1000 (AEST)","from boromir.ozlabs.org (localhost [127.0.0.1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4fx8nM2cvHz2ynC;\n\tThu, 16 Apr 2026 17:30:47 +1000 (AEST)","from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4fx8nL2jzzz2yvc;\n\tThu, 16 Apr 2026 17:30:46 +1000 (AEST)","from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 16 Apr\n 2026 15:30:26 +0800","from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Thu, 16 Apr 2026 15:30:26 +0800"],"ARC-Seal":"i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1776324647;\n\tcv=none;\n b=Qy4KVmrk+z4laWCsulwfZCzJK/P/CicO+pLY0Zg0LTyjazSlU52YNg5fwbtf6DkiIJu/bqLK8m+GSxj2avnZSiwS5RqFxNC4NXPLFhcshe9hQ+SAUy51go/suoR0xgvdjLAsLN9fquyMtMTECSnxFNiVhGvK2Z+Yw8R83HPYgndCmfP0lhkeikoHvQt4TSpyG81w5JkI+ImpHw2Y/P4U8GCd6zwkB/C5WhO0oE0bj7zyxY3epm6PWkbF/FdoJQwG2Te8PbxnBp3NZ5daeQaG5KUiXWkjxtQoD32UpY/Hmk7QmJrL5jW5zayJMocX7V78iiRvb5dQMSox/RgCQLJYFQ==","ARC-Message-Signature":"i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707;\n\tt=1776324647; c=relaxed/relaxed;\n\tbh=ydQUlSGVDJ3UKH7xRkB0Ji0sOcI35bFu0wtDJfeG9Co=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=Un6crV/IJwiqVJ8JrHDuwvnPKHtbtFZG6F/sX0cMS8bpMfXy+1CpEpFsKbO4llMHCaO+LKbGMAV++Nop6xAZlxZL7tkCnPL9cuofldFOn9/n7aKGMqOIZRbBuYaUTAXkVW4NMqcHrJOxXKgqN645Gkbm0Q11XOphOieQ1tog5gWEnAtmRIeLVEJVJqgbE3XR+mwSv0cZVrq77Xm4VMYWity6xTh/f7vpto975fveg+Q7C/v0xKe9ZWJWRf6lN1AedMTTGwGqNce2juMAyxGwHwg6R5b0FVV9teiD7VYx6IOKfSIFl5PzRpX1qGg/qrJc4HCO1FuFdbMdUjir+kCg7Q==","ARC-Authentication-Results":"i=1; lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeedtech.com;\n envelope-from=billy_tsai@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com","From":"Billy Tsai ","Date":"Thu, 16 Apr 2026 15:29:44 +0800","Subject":"[PATCH v7 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe\n AST2700 SCU0","X-Mailing-List":"linux-aspeed@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-ID":"<20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com>","References":"<20260416-upstream_pinctrl-v7-0-d72762253163@aspeedtech.com>","In-Reply-To":"<20260416-upstream_pinctrl-v7-0-d72762253163@aspeedtech.com>","To":"Lee Jones , Rob Herring , \"Krzysztof\n Kozlowski\" , Conor Dooley , \"Joel\n Stanley\" , Andrew Jeffery ,\n\t\"Linus Walleij\" , Billy Tsai ,\n\t\"Bartosz Golaszewski\" , Ryan Chen ","CC":"Andrew Jeffery , ,\n\t, ,\n\t, ,\n\t, ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776324626; l=5303;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=6KEs7OlG92CfANOz1QGj/Gij2ue1APO5MhB7ziqj0qE=;\n b=eVTJqoHgnSga/L7y7lL1Lb+LsMSXnZ0ZjTZl+dWguTNAcFmZS6/Drh7UXo3EsmQFe+geZhWhq\n 8A0U1s00IJLBjJLRnQgCb7tfHgey1F5aF8IR0um1LMbnuvE9Ir4QRUp","X-Developer-Key":"i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=","X-Spam-Status":"No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS\n\tautolearn=disabled version=4.0.1","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org"},"content":"AST2700 consists of two interconnected SoC instances, each with its own\nSystem Control Unit (SCU). The SCU0 provides pin control, interrupt\ncontrollers, clocks, resets, and address-space mappings for the\nSecondary and Tertiary Service Processors (SSP and TSP).\n\nDescribe the SSP/TSP address mappings using the standard\nmemory-region and memory-region-names properties.\n\nDisallow legacy child nodes that are not present on AST2700, including\np2a-control and smp-memram. The latter is unnecessary as software can\naccess the scratch registers via the SCU syscon.\n\nAlso allow the AST2700 SoC0 pin controller to be described as a child\nnode of the SCU0, and add an example illustrating the SCU0 layout,\nincluding reserved-memory, interrupt controllers, and pinctrl.\n\nSigned-off-by: Billy Tsai \n---\n .../bindings/mfd/aspeed,ast2x00-scu.yaml | 113 +++++++++++++++++++++\n 1 file changed, 113 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\nindex a87f31fce019..215ff59b38ea 100644\n--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n@@ -46,6 +46,17 @@ properties:\n '#reset-cells':\n const: 1\n \n+ memory-region:\n+ items:\n+ - description: Region mapped through the first SSP address window.\n+ - description: Region mapped through the second SSP address window.\n+ - description: Region mapped through the TSP address window.\n+ memory-region-names:\n+ items:\n+ - const: ssp-0\n+ - const: ssp-1\n+ - const: tsp\n+\n patternProperties:\n '^p2a-control@[0-9a-f]+$':\n description: >\n@@ -87,6 +98,7 @@ patternProperties:\n - aspeed,ast2400-pinctrl\n - aspeed,ast2500-pinctrl\n - aspeed,ast2600-pinctrl\n+ - aspeed,ast2700-soc0-pinctrl\n \n required:\n - compatible\n@@ -156,6 +168,30 @@ required:\n - '#clock-cells'\n - '#reset-cells'\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ anyOf:\n+ - const: aspeed,ast2700-scu0\n+ - const: aspeed,ast2700-scu1\n+ then:\n+ patternProperties:\n+ '^p2a-control@[0-9a-f]+$': false\n+ '^smp-memram@[0-9a-f]+$': false\n+\n+ - if:\n+ not:\n+ properties:\n+ compatible:\n+ contains:\n+ const: aspeed,ast2700-scu0\n+ then:\n+ properties:\n+ memory-region: false\n+ memory-region-names: false\n+\n additionalProperties: false\n \n examples:\n@@ -180,4 +216,81 @@ examples:\n reg = <0x7c 0x4>, <0x150 0x8>;\n };\n };\n+\n+ - |\n+ / {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ reserved-memory {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ ssp_region_0: memory@400000000 {\n+ reg = <0x4 0x00000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ ssp_region_1: memory@401000000 {\n+ reg = <0x4 0x01000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ tsp_region: memory@402000000 {\n+ reg = <0x4 0x02000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+ };\n+\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ syscon@12c02000 {\n+ compatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n+ reg = <0 0x12c02000 0 0x1000>;\n+ ranges = <0x0 0x0 0x12c02000 0x1000>;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+\n+ memory-region = <&ssp_region_0>, <&ssp_region_1>,\n+ <&tsp_region>;\n+ memory-region-names = \"ssp-0\", \"ssp-1\", \"tsp\";\n+\n+ silicon-id@0 {\n+ compatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n+ reg = <0x0 0x4>;\n+ };\n+\n+ interrupt-controller@1b0 {\n+ compatible = \"aspeed,ast2700-scu-ic0\";\n+ reg = <0x1b0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 97>;\n+ interrupt-controller;\n+ };\n+\n+ interrupt-controller@1e0 {\n+ compatible = \"aspeed,ast2700-scu-ic1\";\n+ reg = <0x1e0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 98>;\n+ interrupt-controller;\n+ };\n+\n+ pinctrl@400 {\n+ compatible = \"aspeed,ast2700-soc0-pinctrl\";\n+ reg = <0x400 0x318>;\n+ emmc-state {\n+ function = \"EMMC\";\n+ groups = \"EMMCG1\";\n+ };\n+ };\n+ };\n+ };\n+ };\n+\n ...\n","prefixes":["v7","2/3"]}