{"id":2223719,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223719/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416014928.1279360-13-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260416014928.1279360-13-jamin_lin@aspeedtech.com>","date":"2026-04-16T01:49:56","name":"[v3,12/17] hw/usb/hcd-ehci: Implement 64-bit siTD descriptor addressing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"cf4c3eaefcf442f17eac0922d4201979ffb7b97d","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/1.1/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416014928.1279360-13-jamin_lin@aspeedtech.com/mbox/","series":[{"id":500066,"url":"http://patchwork.ozlabs.org/api/1.1/series/500066/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500066","date":"2026-04-16T01:49:32","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":3,"mbox":"http://patchwork.ozlabs.org/series/500066/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223719/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223719/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=BqWRd7+B;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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In that mode,\nthe CTRLDSSEGMENT register provides the upper 32 bits that are\nconcatenated with 32-bit link pointer values to form full 64-bit\ndescriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n\nsiTD link pointers are stored as 32-bit values and must be expanded\nto full 64-bit descriptor addresses when 64-bit mode is enabled.\nUpdate the siTD traversal path to use ehci_get_desc_addr() when\nfollowing link pointers.\n\nAppendix B also defines high dword fields for siTD buffer pointers.\nAdd bufptr_hi[] fields to EHCIsitd and use ehci_get_buf_addr() to\nconstruct full 64-bit buffer addresses from bufptr[] and bufptr_hi[]\nwhen processing split isochronous transfers. This allows buffers\nabove 4GB to be handled correctly.\n\nWhen 64-bit capability is disabled, descriptor and buffer addresses\nremain 32-bit and existing behaviour is unchanged.\n\nSigned-off-by: Jamin Lin \n---\n hw/usb/hcd-ehci.h | 1 +\n hw/usb/hcd-ehci.c | 2 +-\n 2 files changed, 2 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\nindex af8c080c60..6406f536e8 100644\n--- a/hw/usb/hcd-ehci.h\n+++ b/hw/usb/hcd-ehci.h\n@@ -109,6 +109,7 @@ typedef struct EHCIsitd {\n #define SITD_BUFPTR_TCNT_MASK 0x00000007\n \n uint32_t backptr; /* Standard next link pointer */\n+ uint32_t bufptr_hi[2];\n } EHCIsitd;\n \n /*\ndiff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\nindex 3db1c25e4d..e1d5ecbad7 100644\n--- a/hw/usb/hcd-ehci.c\n+++ b/hw/usb/hcd-ehci.c\n@@ -1791,7 +1791,7 @@ static int ehci_state_fetchsitd(EHCIState *ehci, int async)\n warn_report(\"Skipping active siTD\");\n }\n \n- ehci_set_fetch_addr(ehci, async, sitd.next);\n+ ehci_set_fetch_addr(ehci, async, ehci_get_desc_addr(ehci, sitd.next));\n ehci_set_state(ehci, async, EST_FETCHENTRY);\n return 1;\n }\n","prefixes":["v3","12/17"]}