{"id":2223718,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223718/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416014928.1279360-12-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260416014928.1279360-12-jamin_lin@aspeedtech.com>","date":"2026-04-16T01:49:55","name":"[v3,11/17] hw/usb/hcd-ehci: Implement 64-bit iTD descriptor addressing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7ce861f2cd09dd441115df05e92d36a5a9b11873","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/1.1/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416014928.1279360-12-jamin_lin@aspeedtech.com/mbox/","series":[{"id":500066,"url":"http://patchwork.ozlabs.org/api/1.1/series/500066/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500066","date":"2026-04-16T01:49:32","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":3,"mbox":"http://patchwork.ozlabs.org/series/500066/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223718/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223718/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=PfNS/YNZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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In that mode,\nthe CTRLDSSEGMENT register provides the upper 32 bits that are\nconcatenated with 32-bit link pointer values to form full 64-bit\ndescriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n\niTD link pointers are stored as 32-bit values and must be expanded\nto full 64-bit descriptor addresses when 64-bit mode is enabled.\nUpdate the iTD traversal path to use ehci_get_desc_addr() when\nfollowing link pointers.\n\nAppendix B also defines high dword fields for iTD buffer pointers.\nAdd bufptr_hi[7] to EHCIitd and use ehci_get_buf_addr() to construct\nfull 64-bit buffer addresses from bufptr[] and bufptr_hi[] fields\nwhen processing isochronous transfers. This allows buffers above\n4GB to be handled correctly.\n\nWhen 64-bit capability is disabled, descriptor and buffer addresses\nremain 32-bit and existing behaviour is unchanged.\n\nSigned-off-by: Jamin Lin \n---\n hw/usb/hcd-ehci.h | 1 +\n hw/usb/hcd-ehci.c | 9 ++++++---\n 2 files changed, 7 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\nindex 712de9d50e..af8c080c60 100644\n--- a/hw/usb/hcd-ehci.h\n+++ b/hw/usb/hcd-ehci.h\n@@ -63,6 +63,7 @@ typedef struct EHCIitd {\n #define ITD_BUFPTR_MAXPKT_SH 0\n #define ITD_BUFPTR_MULT_MASK 0x00000003\n #define ITD_BUFPTR_MULT_SH 0\n+ uint32_t bufptr_hi[7];\n } EHCIitd;\n \n /*\ndiff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\nindex d93d227e6f..3db1c25e4d 100644\n--- a/hw/usb/hcd-ehci.c\n+++ b/hw/usb/hcd-ehci.c\n@@ -1463,7 +1463,8 @@ static int ehci_process_itd(EHCIState *ehci,\n return -1;\n }\n \n- ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);\n+ ptr1 = ehci_get_buf_addr(ehci, itd->bufptr_hi[pg],\n+ itd->bufptr[pg], ITD_BUFPTR_MASK);\n qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as);\n if (off + len > 4096) {\n /* transfer crosses page border */\n@@ -1471,7 +1472,9 @@ static int ehci_process_itd(EHCIState *ehci,\n qemu_sglist_destroy(&ehci->isgl);\n return -1; /* avoid page pg + 1 */\n }\n- ptr2 = (itd->bufptr[pg + 1] & ITD_BUFPTR_MASK);\n+ ptr2 = ehci_get_buf_addr(ehci, itd->bufptr_hi[pg + 1],\n+ itd->bufptr[pg + 1],\n+ ITD_BUFPTR_MASK);\n uint32_t len2 = off + len - 4096;\n uint32_t len1 = len - len2;\n qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);\n@@ -1761,7 +1764,7 @@ static int ehci_state_fetchitd(EHCIState *ehci, int async)\n \n put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,\n sizeof(EHCIitd) >> 2);\n- ehci_set_fetch_addr(ehci, async, itd.next);\n+ ehci_set_fetch_addr(ehci, async, ehci_get_desc_addr(ehci, itd.next));\n ehci_set_state(ehci, async, EST_FETCHENTRY);\n \n return 1;\n","prefixes":["v3","11/17"]}