{"id":2223668,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223668/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415233740.3027321-2-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260415233740.3027321-2-alistair.francis@wdc.com>","date":"2026-04-15T23:37:37","name":"[v2,1/4] target/riscv: Generate access fault if sc comparison fails","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"08880561d47e361c0a5e21fc961391f12bd4a407","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415233740.3027321-2-alistair.francis@wdc.com/mbox/","series":[{"id":500054,"url":"http://patchwork.ozlabs.org/api/1.1/series/500054/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500054","date":"2026-04-15T23:37:38","name":"target/riscv: A collection of bug fixes","version":2,"mbox":"http://patchwork.ozlabs.org/series/500054/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223668/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223668/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Yv40ksUM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwyKS1qzhz1yHP\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 16 Apr 2026 09:39:24 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wD9oD-00037W-Ub; Wed, 15 Apr 2026 19:38:14 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wD9oC-000378-Du\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 19:38:12 -0400","from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wD9o9-0003a6-2S\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 19:38:12 -0400","by mail-pl1-x62a.google.com with SMTP id\n d9443c01a7336-2b2503753efso64593305ad.0\n for <qemu-devel@nongnu.org>; Wed, 15 Apr 2026 16:38:08 -0700 (PDT)","from toolbx.alistair23.me ([2403:581e:fdf9:0:6209:4521:6813:45b7])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b47826ea53sm32341675ad.52.2026.04.15.16.38.02\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 15 Apr 2026 16:38:06 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1776296287; x=1776901087; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Dnq+0tXS4eFr2sdhjjScGLl4PxiJMF49NMAjxhNB8Xw=;\n b=Yv40ksUM0I72HZL87Oyxtu3UPaA0+NUNfxgYBPpFHjQhgKrMvHd8Kr0dUlqj3w4t+g\n 2sophxWUwMVHZhjupOjfhL7APW1RfV9lkHWn2sJ/e7tKFjlUplG+HMbC5PPCKeEXH3Yh\n GE2bCrvTv8kQpObRsWN65I4GFPb98FPDZu1O7Vb8qsCk0ycbMCvlc6egIz+ZHJx7rTaW\n fvmW611wW8B2N5jO3kcgk1t5j0O8PO98euJxRKSwUdxNIqAo9i6UHVxJwydFGXP7UjFx\n biGTS08F4eRVJo2m9g5eYe/XtHG4IDix+1tYqYrgkbpooNWFN7nrd0FRfgL8t1nrIraQ\n 1Nvg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776296287; x=1776901087;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Dnq+0tXS4eFr2sdhjjScGLl4PxiJMF49NMAjxhNB8Xw=;\n b=W9wPPRU6cUIxMBVvKm3PZMZl1tOJjzf1Oe1X1bdp1BGKxoN5/dA/j0vIkqhYeKzDEu\n QiLVF2w4DVmU5VLPKCPKH5sg58wvJ53MabOwfJErYDVPuRe2hfTUDjV8/4ESy8srtb+x\n ikmj4MF2j1zqOQrgqhJqYgPQgds9A4y2gBhbE3deIsZjgD2xfwrRP8uUYPTRKfLjdFj5\n G72IEpnGYNrsBnduajO69o1GKzaPiWI8wA6yxBiP8VraXoVjDftwgAlapyHD6o/3g/X4\n +VFKG8/8tpu5Gm1JSLwA1BWo9JDCRri8bLdb0Q+41n1/uKudxLXHXpoHmbyqW3MDiA9b\n ia5g==","X-Forwarded-Encrypted":"i=1;\n AFNElJ9CQgeyT4DIJQOiQ/5YI3rLwz3zFakp5fzCTEaiIwwqfCyectod/CUjnW7E/21PYJB08PyuHRpnmlVD@nongnu.org","X-Gm-Message-State":"AOJu0YzzrhhPMQwKpOnHnRknbyBKuJjper3dyJ/B2mnZhq7YNlmlwdCR\n EtvYuQfRIyd1yM71/R6o8CEvvCaEYDkF1gjlgKK7nFZ9j6V9KuM+8h67","X-Gm-Gg":"AeBDieuqt+Nq0RnJYrTJyX60uxAGUg/AP5vTQz/LnDECmbzeZvaEL/s4WthlE9PZOZO\n Fglbp4eeVCDz7WFWQ8lidgH439WKvA/M/nPDloOF8/SaoO36zXgdXUX4skHF9QCLN7Ro2VV7GmT\n E29m+twqvRjAEWieWEOaKj49Il6yF9P/NaxvnYP40tX2fv8QJumV1YfHRPz2rnY2ARB987LHpxm\n sum9mIIRq+E/uPb+Ni0UXMvAIOTl2JdHRddYetJN5Bwa+rkEkrn7fL+GaOuMB5vMnGKqR508Y1l\n WYgHyrDqkBpUxB7xgxEe1KFwHfBaPJDn8Chy/VSbxTPfplWZCdBtVpu8/YyIe5tpuWHr9llNAmf\n flA5yRqVv+cWjXhkCKCdenaiy7L6ZfDX7eoZj1W6JF1qLg/FDWjudXv16ABY4GbuI+JSjqwUIaH\n Z0YIUFUG0dYbOrbs6AVg02fDELflUpWedvfwuJZiXT","X-Received":"by 2002:a17:902:76c3:b0:2b0:52b7:e82 with SMTP id\n d9443c01a7336-2b2d59a49fbmr183354235ad.16.1776296287400;\n Wed, 15 Apr 2026 16:38:07 -0700 (PDT)","From":"alistair23@gmail.com","X-Google-Original-From":"alistair.francis@wdc.com","To":"palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org","Cc":"alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,\n qemu-stable@nongnu.org","Subject":"[PATCH v2 1/4] target/riscv: Generate access fault if sc comparison\n fails","Date":"Thu, 16 Apr 2026 09:37:37 +1000","Message-ID":"<20260415233740.3027321-2-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260415233740.3027321-1-alistair.francis@wdc.com>","References":"<20260415233740.3027321-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62a;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Alistair Francis <alistair.francis@wdc.com>\n\nThe RISC-V spec states:\n\n\"For the purposes of memory protection, a failed SC.W may be treated\nlike a store.\"\n\nSo if the comparison in sc.w fails we should still check for alignment\nand do a probe access to check permissions.\n\nCc: qemu-stable@nongnu.org\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3323\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3136\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\n---\n target/riscv/helper.h                   |  3 +++\n target/riscv/op_helper.c                | 14 ++++++++++++++\n target/riscv/insn_trans/trans_rva.c.inc |  6 ++++++\n 3 files changed, 23 insertions(+)","diff":"diff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex b785456ee0..fa16ab2b82 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -1289,3 +1289,6 @@ DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32)\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_1(ssamoswap_disabled, void, env)\n #endif\n+\n+/* Zalrsc SC write probe */\n+DEF_HELPER_FLAGS_3(sc_probe_write, TCG_CALL_NO_WG, void, env, tl, tl)\ndiff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c\nindex 6ccc127c30..b569366369 100644\n--- a/target/riscv/op_helper.c\n+++ b/target/riscv/op_helper.c\n@@ -281,6 +281,20 @@ void helper_cbo_inval(CPURISCVState *env, target_ulong address)\n     /* We don't emulate the cache-hierarchy, so we're done. */\n }\n \n+void helper_sc_probe_write(CPURISCVState *env, target_ulong addr,\n+                           target_ulong size)\n+{\n+    uintptr_t ra = GETPC();\n+    int mmu_idx = riscv_env_mmu_index(env, false);\n+\n+    if (addr & (size - 1)) {\n+        env->badaddr = addr;\n+        riscv_raise_exception(env, RISCV_EXCP_STORE_AMO_ADDR_MIS, ra);\n+    }\n+\n+    probe_write(env, addr, size, mmu_idx, ra);\n+}\n+\n #ifndef CONFIG_USER_ONLY\n \n target_ulong helper_sret(CPURISCVState *env)\ndiff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc\nindex a7a3278d24..62c0fe673d 100644\n--- a/target/riscv/insn_trans/trans_rva.c.inc\n+++ b/target/riscv/insn_trans/trans_rva.c.inc\n@@ -90,6 +90,12 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)\n      */\n     TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;\n     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);\n+    /*\n+     * \"For the purposes of memory protection, a failed SC.W may be treated\n+     * like a store.\" so let's check the write access permissions\n+     */\n+    gen_helper_sc_probe_write(tcg_env, src1,\n+                              tcg_constant_tl(memop_size(mop)));\n     gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));\n \n     gen_set_label(l2);\n","prefixes":["v2","1/4"]}