{"id":2223652,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223652/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415215539.92629-8-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260415215539.92629-8-philmd@linaro.org>","date":"2026-04-15T21:55:38","name":"[7/8] target/mips: Reduce CPUState scope when used with CPU_FOREACH()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"eca877668c3238eed64a5a806af7b74a868558a2","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415215539.92629-8-philmd@linaro.org/mbox/","series":[{"id":500043,"url":"http://patchwork.ozlabs.org/api/1.1/series/500043/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500043","date":"2026-04-15T21:55:33","name":"cocci: Do not initialize variable used by *FOREACH*() macro","version":1,"mbox":"http://patchwork.ozlabs.org/series/500043/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223652/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223652/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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(PDT)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org,\n qemu-block@nongnu.org","Subject":"[PATCH 7/8] target/mips: Reduce CPUState scope when used with\n CPU_FOREACH()","Date":"Wed, 15 Apr 2026 23:55:38 +0200","Message-ID":"<20260415215539.92629-8-philmd@linaro.org>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260415215539.92629-1-philmd@linaro.org>","References":"<20260415215539.92629-1-philmd@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com","X-Spam_score_int":"4","X-Spam_score":"0.4","X-Spam_bar":"/","X-Spam_report":"(0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1,\n DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When possible, reduce CPUState variable scope.\nPrefer cpu_env(cpu) over &cpu->env.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/internal.h | 11 ++++++-----\n target/mips/tcg/system/cp0_helper.c | 28 ++++++++++++++++------------\n target/mips/tcg/system/tlb_helper.c | 7 +++----\n 3 files changed, 25 insertions(+), 21 deletions(-)","diff":"diff --git a/target/mips/internal.h b/target/mips/internal.h\nindex c6cf69dfb6a..cc031662ef9 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -279,7 +279,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)\n \n static inline int mips_vp_active(CPUMIPSState *env)\n {\n- CPUState *other_cs;\n+ CPUState *cs;\n \n /* Check if the VP disabled other VPs (which means the VP is enabled) */\n if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\n@@ -287,10 +287,11 @@ static inline int mips_vp_active(CPUMIPSState *env)\n }\n \n /* Check if the virtual processor is disabled due to a DVP */\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n- if ((&other_cpu->env != env) &&\n- ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n+ CPU_FOREACH(cs) {\n+ CPUMIPSState *other_env = cpu_env(cs);\n+\n+ if ((other_env != env) &&\n+ ((other_env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n return 0;\n }\n }\ndiff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c\nindex 99f43ad9e11..4ec1312f016 100644\n--- a/target/mips/tcg/system/cp0_helper.c\n+++ b/target/mips/tcg/system/cp0_helper.c\n@@ -1559,12 +1559,13 @@ target_ulong helper_emt(void)\n \n target_ulong helper_dvpe(CPUMIPSState *env)\n {\n- CPUState *other_cs;\n target_ulong prev = env->mvp->CP0_MVPControl;\n \n if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n+ CPUState *cpu;\n+\n+ CPU_FOREACH(cpu) {\n+ MIPSCPU *other_cpu = MIPS_CPU(cpu);\n /* Turn off all VPEs except the one executing the dvpe. */\n if (&other_cpu->env != env) {\n other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);\n@@ -1577,12 +1578,13 @@ target_ulong helper_dvpe(CPUMIPSState *env)\n \n target_ulong helper_evpe(CPUMIPSState *env)\n {\n- CPUState *other_cs;\n target_ulong prev = env->mvp->CP0_MVPControl;\n \n if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n+ CPUState *cpu;\n+\n+ CPU_FOREACH(cpu) {\n+ MIPSCPU *other_cpu = MIPS_CPU(cpu);\n \n if (&other_cpu->env != env\n /* If the VPE is WFI, don't disturb its sleep. */\n@@ -1599,12 +1601,13 @@ target_ulong helper_evpe(CPUMIPSState *env)\n /* R6 Multi-threading */\n target_ulong helper_dvp(CPUMIPSState *env)\n {\n- CPUState *other_cs;\n target_ulong prev = env->CP0_VPControl;\n \n if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n+ CPUState *cpu;\n+\n+ CPU_FOREACH(cpu) {\n+ MIPSCPU *other_cpu = MIPS_CPU(cpu);\n /* Turn off all VPs except the one executing the dvp. */\n if (&other_cpu->env != env) {\n mips_vpe_sleep(other_cpu);\n@@ -1617,12 +1620,13 @@ target_ulong helper_dvp(CPUMIPSState *env)\n \n target_ulong helper_evp(CPUMIPSState *env)\n {\n- CPUState *other_cs;\n target_ulong prev = env->CP0_VPControl;\n \n if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n+ CPUState *cpu;\n+\n+ CPU_FOREACH(cpu) {\n+ MIPSCPU *other_cpu = MIPS_CPU(cpu);\n if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {\n /*\n * If the VP is WFI, don't disturb its sleep.\ndiff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c\nindex 680b4da29fa..8537798a53f 100644\n--- a/target/mips/tcg/system/tlb_helper.c\n+++ b/target/mips/tcg/system/tlb_helper.c\n@@ -346,15 +346,14 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)\n uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);\n uint8_t invMsgR = 0;\n uint32_t invMsgMMid = env->CP0_MemoryMapID;\n- CPUState *other_cs;\n+ CPUState *cpu;\n \n #ifdef TARGET_MIPS64\n invMsgR = extract64(arg, 62, 2);\n #endif\n \n- CPU_FOREACH(other_cs) {\n- MIPSCPU *other_cpu = MIPS_CPU(other_cs);\n- global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,\n+ CPU_FOREACH(cpu) {\n+ global_invalidate_tlb(cpu_env(cpu), invMsgVPN2, invMsgR, invMsgMMid,\n invAll, invVAMMid, invMMid, invVA);\n }\n }\n","prefixes":["7/8"]}