{"id":2223648,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2223648/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415215539.92629-7-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260415215539.92629-7-philmd@linaro.org>","date":"2026-04-15T21:55:37","name":"[6/8] cocci: Do not initialize variable used by CPU_FOREACH macro","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b8f1ff49ac6d72d1c2aea7f5daa585e8fbb716b6","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.1/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415215539.92629-7-philmd@linaro.org/mbox/","series":[{"id":500043,"url":"http://patchwork.ozlabs.org/api/1.1/series/500043/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500043","date":"2026-04-15T21:55:33","name":"cocci: Do not initialize variable used by *FOREACH*() macro","version":1,"mbox":"http://patchwork.ozlabs.org/series/500043/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223648/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223648/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=PjHFefcN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::336;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com","X-Spam_score_int":"4","X-Spam_score":"0.4","X-Spam_bar":"/","X-Spam_report":"(0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1,\n DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The CPU_FOREACH() macro, defined in \"hw/core/cpu.h\",\nends up calling QTAILQ_FOREACH_RCU() which always\nassigns its iterator variable when entering the loop.\nRemove the pointless and possibly misleading assignment.\n\nMechanical patch using the following coccinelle spatch:\n\n @@\n type T;\n identifier e;\n iterator FOREACH_MACRO =~ \".*_FOREACH.*\";\n statement S;\n @@\n - T *e = ...;\n + T *e;\n ... when != e\n FOREACH_MACRO(e, ...) S\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/internal.h | 2 +-\n hw/misc/mips_cpc.c | 4 ++--\n target/mips/tcg/system/cp0_helper.c | 8 ++++----\n target/mips/tcg/system/tlb_helper.c | 2 +-\n 4 files changed, 8 insertions(+), 8 deletions(-)","diff":"diff --git a/target/mips/internal.h b/target/mips/internal.h\nindex 28eb28936ba..c6cf69dfb6a 100644\n--- a/target/mips/internal.h\n+++ b/target/mips/internal.h\n@@ -279,7 +279,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)\n \n static inline int mips_vp_active(CPUMIPSState *env)\n {\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n \n /* Check if the VP disabled other VPs (which means the VP is enabled) */\n if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\ndiff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c\nindex 924de855ee2..240ccf4d312 100644\n--- a/hw/misc/mips_cpc.c\n+++ b/hw/misc/mips_cpc.c\n@@ -44,7 +44,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)\n \n static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)\n {\n- CPUState *cs = first_cpu;\n+ CPUState *cs;\n \n CPU_FOREACH(cs) {\n uint64_t i = 1ULL << cs->cpu_index;\n@@ -62,7 +62,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)\n \n static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)\n {\n- CPUState *cs = first_cpu;\n+ CPUState *cs;\n \n CPU_FOREACH(cs) {\n uint64_t i = 1ULL << cs->cpu_index;\ndiff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/cp0_helper.c\nindex b69e70d7fcf..99f43ad9e11 100644\n--- a/target/mips/tcg/system/cp0_helper.c\n+++ b/target/mips/tcg/system/cp0_helper.c\n@@ -1559,7 +1559,7 @@ target_ulong helper_emt(void)\n \n target_ulong helper_dvpe(CPUMIPSState *env)\n {\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n target_ulong prev = env->mvp->CP0_MVPControl;\n \n if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {\n@@ -1577,7 +1577,7 @@ target_ulong helper_dvpe(CPUMIPSState *env)\n \n target_ulong helper_evpe(CPUMIPSState *env)\n {\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n target_ulong prev = env->mvp->CP0_MVPControl;\n \n if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {\n@@ -1599,7 +1599,7 @@ target_ulong helper_evpe(CPUMIPSState *env)\n /* R6 Multi-threading */\n target_ulong helper_dvp(CPUMIPSState *env)\n {\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n target_ulong prev = env->CP0_VPControl;\n \n if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {\n@@ -1617,7 +1617,7 @@ target_ulong helper_dvp(CPUMIPSState *env)\n \n target_ulong helper_evp(CPUMIPSState *env)\n {\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n target_ulong prev = env->CP0_VPControl;\n \n if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {\ndiff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c\nindex 566924b079e..680b4da29fa 100644\n--- a/target/mips/tcg/system/tlb_helper.c\n+++ b/target/mips/tcg/system/tlb_helper.c\n@@ -346,7 +346,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)\n uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);\n uint8_t invMsgR = 0;\n uint32_t invMsgMMid = env->CP0_MemoryMapID;\n- CPUState *other_cs = first_cpu;\n+ CPUState *other_cs;\n \n #ifdef TARGET_MIPS64\n invMsgR = extract64(arg, 62, 2);\n","prefixes":["6/8"]}